Md Tawfiq Amin
Military Institute of Science & Technology (MIST), EECE, Faculty Member
- Md Tawfiq Amin received his Ph.D. degree from University of Macau, Macao SAR, China (in the field of Microelectronics... moreMd Tawfiq Amin received his Ph.D. degree from University of Macau, Macao SAR, China (in the field of Microelectronics – Wireless research line) under the State Key Lab of Analog and Mixed-Signal VLSI Laboratory. He received the B.Sc. degree (with highest honors) in Electrical and Electronic Engineering from KUET, Khulna, Bangladesh, in 2005, and the M. Phil degree in Electronic Engineering from City University of Hong Kong (CityU), Hong Kong, in 2009. He held position of Lecturer at the dept of EEE, KUET (2005~2006). Currently he is a faculty member at Military Institute of Science and Technology (MIST), Dhaka, Bangladesh. His current research includes analog and RF integrated circuit design for wireless applications.edit
A highly efficient three-stage 2.8 GHz fully-integrated Si power amplifier (PA) using 90 nm CMOS process for IoT applications is reported in this work. The designed PA exhibits a simulated output power of 20.33 dBm, gain of 20.27 dB and... more
A highly efficient three-stage 2.8 GHz fully-integrated Si power amplifier (PA) using 90 nm CMOS process for IoT applications is reported in this work. The designed PA exhibits a simulated output power of 20.33 dBm, gain of 20.27 dB and 32.74% power added efficiency (PAE). This fully integrated PA achieves feasible frequency performance for critical IoT range. This paper addresses the potential for the incorporation of not only linear but also highly efficient PA architectures at GHz frequencies into nanometer CMOS technologies. The performances of the proposed design are then compared with other referred power amplifier circuits. It can be noticed that this proposed design exhibits outstanding performance incase of PAE and power gain. Three-stage PA is proposed targeting the 802.11n WLAN protocol that operates in the 2.8 GHz frequency band with strict linearity specifications.
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ABSTRACT
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Abstract This paper presents a tunable active inductor based ultra-low power, low area voltage-controlled oscillator (VCO) in 90 nm CMOS process. In the designed VCO, the modified topology of the active inductor is employed along with... more
Abstract This paper presents a tunable active inductor based ultra-low power, low area voltage-controlled oscillator (VCO) in 90 nm CMOS process. In the designed VCO, the modified topology of the active inductor is employed along with tuning capability. The layoutbased simulation has been performed deeming parasitic resistances and capacitances. The designed VCO yields an oscillation frequency ranging from 1.38 GHz to 3.16 GHz with a tuning range of 78.41%, where the tuning voltage is driven from 0.4 V to −0.2 V. The power dissipation varies from 0.062 mW to 0.177 mW, and the VCO provides a differential output power of 8.34 dBm to 3.94 dBm. The phase noise varies from −71 dBc/Hz to −65.4 dBc/Hz, and the Figure of Merit (FoM) has a value of −143.09 dBc/Hz @ 2.79 GHz frequency. The process corner analysis, temperature swept analysis, and Monte Carlo analysis of the proposed VCO had been carried out for the evaluation of its compatibility for diversified environments. Furthermore, the exclusion of the MOS varactor has condensed total silicon area consumption (10.3 μm × 8.5 μm). Finally, the designed VCO's performance parameters have been compared with mentioned designs where it is demonstrated that the designed VCO outdoes the others in most cases along with outstanding outcomes of low power and low silicon area consumption.
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In this paper, a cross coupled rectifier is proposed and studied for Radio Frequency (RF) energy harvesting with wide frequency range. Threshold voltage of the MOS transistor is one of the major barriers of RF to DC converter. In this... more
In this paper, a cross coupled rectifier is proposed and studied for Radio Frequency (RF) energy harvesting with wide frequency range. Threshold voltage of the MOS transistor is one of the major barriers of RF to DC converter. In this work the usage of an auxiliary MOSFET mechanism and storage capacitors to eliminate threshold voltage effect in MOS transistor is recommended, which drastically increases the DC extraction capability of charge pump. The proposed rectifier is designed and simulated in 90 nm CMOS process and simulation results exhibit a high power conversion efficiency (PCE) of 78.5% for $10 k \Omega$ load. The proposed circuit also gives a same output voltage from 915 MHz to 2.45 GHz. The results also show that the rectifier is insensitive to temperature and process corners. The rectifier can be used in numerous RF energy harvesting system, including RFID applications and other wireless applications.
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Voltage controlled oscillator (VCO) is one of the key components required for the wireless communication systems. In this paper a low power, low phase noise 3-stage differential ring VCO is designed for passive Radio Frequency... more
Voltage controlled oscillator (VCO) is one of the key components required for the wireless communication systems. In this paper a low power, low phase noise 3-stage differential ring VCO is designed for passive Radio Frequency Identification (RFID) transponders in microwave frequency range that is compatible with Zigbee, IEEE 802.11 b/g and Bluetooth protocols. 90 nm CMOS technology is adopted and the simulations of the designed VCO is performed in Cadence virtuoso environment. Simulation results show that it has wide tuning range from 1.04 GHz to 4.21 GHz (120.7%) and the power consumption is 2.27 mW at 2.45 GHz. The oscillator has a phase noise from -92.01 dBc/Hz to -86.90 dBc/Hz at 1 MHz offset frequency. At 2.45 GHz oscillation frequency the figure-of-merit (FOM) has a value of –153.35 dBc/Hz. Additionally, to assess the VCO in diversified environments process corner analysis, temperature sweeping, Monte Carlo analysis and stability analysis has been performed. Although the proposed VCO is designed for passive RFID tags, the architecture is suitable for many other wireless applications for microwave frequency.
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This paper proposes a digitally controlled Quadrature voltage-controlled oscillator (QVCO) having a tuning scope of S. 1S$\sim$12.57 GHz, mainly applicable for X band frequency implementations in 90 nm CMOS process. 4-bits MOS varactor... more
This paper proposes a digitally controlled Quadrature voltage-controlled oscillator (QVCO) having a tuning scope of S. 1S$\sim$12.57 GHz, mainly applicable for X band frequency implementations in 90 nm CMOS process. 4-bits MOS varactor based digitally controlling scheme has been employed, which outputs 16 separate frequencies. Phase noise @ lMHz offset varies from -122.47dBc/Hz to -99dBc/Hz, and the output power alters from 9.92 dBm to 7.99 dBm. The Maximum Figure of merit is -190.40dBc/Hz for 8.18 GHz frequency, and the DC power consumption is 10.75 mW. We have also done process corner analysis, temperature sweep analysis, and Monte Carlo simulation of the proposed design for perfect justification. Finally, a fair comparison has also been shown in tabular format for basic performance parameters.
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This paper presents an area efficient and low phase noise charge pump in 90nm CMOS technology. The non-linearity effects of conventional charge pump are endeavored to improve in this model. Instead of using an op-amp, the cascade... more
This paper presents an area efficient and low phase noise charge pump in 90nm CMOS technology. The non-linearity effects of conventional charge pump are endeavored to improve in this model. Instead of using an op-amp, the cascade technique is applied to reduce current mismatch, whose performance is analyzed using temperature swept analysis, process corner analysis and Monte Carlo analysis. The proposed charge pump occupied $27.04\mu m^{2}$ silicon area in layout design with de power consumption $34.0965\ \mu \mathrm{W}$ from the supply voltage of 1V. Finally, comparing with the state-of-art, the presented charge pump exposes a better performance in terms of low dc power consumption, low phase noise and less active layout area.
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This paper presents a power-efficient LC VCO model for D band wireless applications in 90 nm CMOS technology. An area efficient design of the proposed model is ensured by avoiding the requirement of additional capacitor for LC tank and... more
This paper presents a power-efficient LC VCO model for D band wireless applications in 90 nm CMOS technology. An area efficient design of the proposed model is ensured by avoiding the requirement of additional capacitor for LC tank and varactor utilizing the parasitic capacitance of MOSs. The performance of the model is evaluated and its compatibility is analyzed using the process comer analysis, temperature swept analysis, Monte Carlo analysis and stability analysis in multifarious environments. An oscillation frequency from 163.25 GHz to 172.77 GHz is obtained with the applied tuning voltage ranged from 0.5 V to 1.1 V. Consuming a low DC power (2.82 – 2.96) mW, the proposed VCO provides relatively high output power on its differential terminal having the value of 15.53 dBm to 6.43 dBm. The phase noise varies from –92.99 dBc/Hz to –75.81 dBc/Hz and the figure of merit has a value of –188.67 dBc/Hz at 164.39 GHz. Finally, comparing with the state-of-art VCO models, the presented model has demonstrated a better performance in terms of low DC power consumption, high output power and a better figure of merit.
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This work presented here a dissertation which proposed a quadrature voltage-controlled oscillator (QVCO) based on tunable active inductor for IEEE 802.11b applications in 90nm CMOS process. The designed QVCO achieves an oscillation... more
This work presented here a dissertation which proposed a quadrature voltage-controlled oscillator (QVCO) based on tunable active inductor for IEEE 802.11b applications in 90nm CMOS process. The designed QVCO achieves an oscillation frequency of tuning ranges from 2.25GHz to 3.25GHz having tuning scope of 36.36%, while varying tuning voltages ranging from 0.4V to 0.8V. The QVCO provides a differential output power of 0.933dBm to −2.67dBm. The simulated phase noise varies from −85.25dBc/Hz to −80.92dBc/Hz and the QVCO exhibits DC power consumption of 1.82mW to 4.05mW. Figure of merit (FoM) of −148.99dBc/Hz observed @ 2.77GHz frequency. Moreover, a systematic analysis of QVCO on various techniques such as process corner analysis (SS, SF, FS &FF), Monte Carlo simulation (for process variation & mismatch), temperature swept analysis and stability analysis are performed to determine the design's compatibility in multifarious environment. Finally, the proposed design's performance parameters are compared with other references in a tabular form and the comparison shows that the state-of-arts outdo most of the mentions.
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This paper presents the comparative analysis of active inductor design for high quality factor at high frequency applications on the selection of active inductor topologies. Inductor based circuits are commonly used in integrated circuits... more
This paper presents the comparative analysis of active inductor design for high quality factor at high frequency applications on the selection of active inductor topologies. Inductor based circuits are commonly used in integrated circuits where the quality factor of the inductor dominates the performance of the designed circuits. Since planner spiral inductor occupies a large area and shows low quality factor, active inductor is a good option to overcome the drawbacks of the spiral inductors. This paper summarizes the analysis and simulation results to select the best active inductor topology for high quality factor at high frequency applications (RF applications). Simulated in Cadence 6.16 environment using the 90 nm CMOS technology, Weng-Kuo active inductor topology shows the higher quality factor as well as high frequency range.
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This paper presents an active inductor based voltage-controlled oscillator (VCO) design by most commonly used NMOS cross-coupled LC-tank topology. Differential configuration of active inductor is formed by two single ended active... more
This paper presents an active inductor based voltage-controlled oscillator (VCO) design by most commonly used NMOS cross-coupled LC-tank topology. Differential configuration of active inductor is formed by two single ended active inductors which provide a high Q factor within the tuning range. The tuning range of the designed VCO is 2.17GHz to 2.72GHz (22.49{\%}) with a low power consumption of 4.18761mW. The phase noise is -82.34 dBC/Hz at 2.4 GHz and FOM is -143.4 dBC/Hz at 1MHz frequency offset. Compared with the state-of-the-art, the designed active inductor based VCO provides high differential output power (2.158 dBm to 3.162 dBm) with a stable figure of merit (FOM) within the tuning range that outperform the other cited designs.
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This paper presents a simple strategy of optimizing frequency dispersion and power consumption of CMOS ring oscillator which can be used to transmit power through the human body at 13.5 MHz and reduce the size of the implant. Three-stage... more
This paper presents a simple strategy of optimizing frequency dispersion and power consumption of CMOS ring oscillator which can be used to transmit power through the human body at 13.5 MHz and reduce the size of the implant. Three-stage ring oscillator is designed using MOS capacitor in the output of each delay cell and added resistor to improve frequency stability. A supply voltage of 1V is used in the simulation whereas the control voltage varies from 0V to 0.6V. In the simulation, 90nm CMOS process technology has been used. A linear tuning characteristic has been accomplished ranging from 12 MHz to 25 MHz in the interest of wireless applications. The circuit shows an exceptionally steady output waveform in various parameters with exceptionally low power consumption of 53.4 µW. The phase noise (-125 dBc/Hz) is pretty good taking into account the higher oscillation frequency of the circuit.
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This paper comprises a 4.94 to 5. 35 GHz digitally tuned bandpass filter based on 4-bit scheme which outputs 16 different frequencies for the corresponding bit combinations. Active inductor is employed considering several effective... more
This paper comprises a 4.94 to 5. 35 GHz digitally tuned bandpass filter based on 4-bit scheme which outputs 16 different frequencies for the corresponding bit combinations. Active inductor is employed considering several effective utilization such as area consumption and inductive tunability. Array of MOS capacitor is employed to tune inductance, finally, the center frequency. Simulated in $90 nm$ CMOS, the forward gain (S21) changes from $8.86 \sim 17.76 dB$ within the tuning range while in case of return loss $(S11)$ it is $-21.43 \sim-12.23 dB$. The DC power consumption is always kept at $3.93 mW$ and the noise Figure alters from $18.86 dB \sim 19.48$ dB. Process corner analysis, temperature sweep analysis, and Monte Carlo simulation is performed to illustrate the viability of proposed design. The compact layout shows that the BPF occupies an area of $826 \mu m^{2}$. Finally, a fair comparison has been performed with respect to other published works based on the fundamental performance parameters. The frequency range includes 5 GHz frequency spectrum which is highly preferable for today’s wireless LAN applications.
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This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90[Formula: see text]nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of... more
This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90[Formula: see text]nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46[Formula: see text]GHz for the tuning voltage of 0.3–1.5[Formula: see text]V. It consumes a low dc power ranging from 2.44[Formula: see text]mW to 4.79[Formula: see text]mW for the specified tuning range. The variation of phase noise ranges from [Formula: see text][Formula: see text]dBc/Hz to [Formula: see text][Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of [Formula: see text][Formula: see text]dBc/Hz with a differential output power of 1.8[Formula: see text]dBm at tuning voltage of 0.7[Formula: see text]V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation ...
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This paper presents an approach by which common components can be shared within two separate analog blocks. Here, we have utilized two separate blocks i.e., oscillator and low noise amplifier (LNA). Both of them has the common LC tank... more
This paper presents an approach by which common components can be shared within two separate analog blocks. Here, we have utilized two separate blocks i.e., oscillator and low noise amplifier (LNA). Both of them has the common LC tank which are shared through SPDT switching system. The noteworthy outcome will be significant reduction of silicon area consumption due to the sharing. Finally, we have shown a comparison on how the introduction of SPDT system affects the performance of oscillator or LNA. We have demonstrated the comparison through depictions and tabular forms.
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The use of ultra-wideband (UWB) in target detection, radar and wireless connectivity, specifically in the medical world, has attracted a lot of attention. The concept that the IR-UWB system does not necessarily require carrier signals is... more
The use of ultra-wideband (UWB) in target detection, radar and wireless connectivity, specifically in the medical world, has attracted a lot of attention. The concept that the IR-UWB system does not necessarily require carrier signals is one of its most appealing features. IR-UWB can transmit information using short Gaussian monocycle pulses. In light of these advantages, this paper proposes a novel UWB transmitter system which consists of UWB signal generating circuits and UWB antenna, which work together to create entire UWB transmitter. It is based on impulses and has a simple architecture with low power consumption. The proposed transmitter is realized in Cadence tools with 90nm CMOS technology and proposed UWB antenna is simulated using Advanced Design System (ADS) simulator software. In addition, the transmitter circuit and the antenna are co-simulated using ADS software. The illustrated UWB transmitter uses a low-power supply and generates pulse amplitude with pulse duration of for the Gaussian monocycle pulse. Due to its increased output voltage swing and reduced power consumption when comparing to other circuits, the proposed architecture is functional and suitable for use in short-range wireless networks and medical applications.
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Research Interests: Engineering, Mathematics, Computer Science, Technology, Signal Processing, and 12 moreDigital Signal Processing, Parameter estimation, Maximum Likelihood, LINEAR PREDICTIVE CODING, Frequency Estimation, Gaussian noise, Signal Process, Offset, Signal to Noise Ratio, Linear Prediction, maximum likelihood estimate, and Iterative Quadratic Maximum Likelihood (IQML)
Research Interests: Signal Processing, Digital Signal Processing, Parameter estimation, Cramer Rao Lower Bound, Wave Equations, and 8 moreWave Equation, Maximum Likelihood Estimation, LINEAR PREDICTIVE CODING, Gaussian noise, Boolean Satisfiability, Electrical And Electronic Engineering, Linear Prediction, and maximum likelihood estimate
This paper presents active inductor based VCO design for wireless applications based on analysis of active inductor models (Weng-Kuo Cascode active inductor & Liang Regular Cascode active inductor) with feedback resistor technique.... more
This paper presents active inductor based VCO design for wireless applications based on analysis of active inductor models (Weng-Kuo Cascode active inductor & Liang Regular Cascode active inductor) with feedback resistor technique. Embedment of feedback resistor results in the increment of inductance as well as the quality factor whereas the values are 125.6@2.4GHz (Liang) and 98.7@3.4GHz (Weng- Kuo). The Weng-Kuo active inductor based VCO shows a tuning frequency of 1.765GHz ~2.430GHz (31.7%), while consuming a power of 2.60 mW and phase noise of -84.15 dBc/Hz@1MHz offset. On the other hand, Liang active inductor based VCO shows a frequency range of 1.897GHz ~2.522GHz (28.28%), while consuming a power of 1.40 mW and phase noise of -80.79 dBc/Hz@1MHz offset. Comparing Figure-of-Merit (FoM), power consumption, output power and stability in performance, designed active inductor based VCOs outperform with the state-of-the-art.
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This article proposes a tunable active inductor (AI)-based voltage-controlled oscillator (VCO) andbandpass filters (BPF) on a single integrated design in 90 nm CMOS process for wireless applications. By exploiting component sharing... more
This article proposes a tunable active inductor (AI)-based voltage-controlled oscillator (VCO) andbandpass filters (BPF) on a single integrated design in 90 nm CMOS process for wireless applications. By exploiting component sharing technique through single pole double throws switching method, a common AI is shared between VCO and BPFs. As the passive inductor is replaced by the AI and shared, silicon area consumption is significantly reduced. Transforming the inductor in tunable mode benefits to eliminate MOS varactors for tuning purposes ; one step forward to reduce silicon area consumption. Operating as VCO, its frequency ranges from 1.93 to 6.22 GHz (tuning scope is 105%) for tuning voltage of 0.2 ∼ 1 V. The DC power consumption varies from 1.83 to 3.84 mW, and differential output power is 3.39 to − 2.99 dBm. The phase noise varies from − 81.32 to − 76.89 dBc/Hz, and the figure of merit has a value of − 148.74 dBc/Hz at 5.03 GHz frequency. While acting as BPF, two approaches of center frequency tuning are applied. The voltage tuning yields center frequency of 8.43 ∼ 7.08 GHz along with the maximum gain of 10.29 dB at 7.81 GHz. The capacitive tuning outputs frequency tuning of 7.64 ∼ 7.06 GHz. The BPF consumes DC power of 2.56 to 2.27 mW (voltage tuning) and 2.40 mW (capacitive tuning). The proposed design occupies a layout area of 1215.6 μm 2. All the simulations have been performed considering parasitic elements evolved from the extraction of layout. Finally, a quantitative comparison and justification of the proposed design are made with respect to other published works. K E Y W O R D S active inductor, BPF, DC power consumption, frequency, phase noise, VCO 1 INTRODUCTION The acceleration of leading-edge communication systems is making performance efficient radio frequency integrated circuits (RFICs) highly demandable. Voltage-controlled oscillators (VCOs) with extensive tuning range are fundamental blocks of almost all RFICs for multiband and multi-standard applications. 1 In the evolving era of Internet of things (IoT), This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.
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This paper describes an ultra-low-voltage low-power 8-phase voltage-controlled oscillator (VCO) for 10GHz beam-forming satellite receivers. It is composed by four 0.5V current-reuse LC-VCO cells interlocked by direct-back-gate coupling,... more
This paper describes an ultra-low-voltage low-power 8-phase voltage-controlled oscillator (VCO) for 10GHz beam-forming satellite receivers. It is composed by four 0.5V current-reuse LC-VCO cells interlocked by direct-back-gate coupling, featuring independent sizing of coupling strength and frequency tuning, while avoiding the risk of forward bias the substrate p-n junctions. Optimized in 65nm CMOS, the 8-phase VCO draws only 2mW. The phase noise at 1MHz offset is-114dBc/Hz to-110dBc/Hz over a 32.5% tuning range from 8.55 to 11.88GHz. These results correspond to a high-and-stable FOM within-188 to-189.5dBc/Hz.
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The problem of parameter estimation of a single sinusoid with unknown offset in additive Gaussian noise is addressed. After deriving the linear prediction property of the noise-free signal, the maximum likelihood estimator for the... more
The problem of parameter estimation of a single sinusoid with unknown offset in additive Gaussian noise is addressed. After deriving the linear prediction property of the noise-free signal, the maximum likelihood estimator for the frequency parameter is developed. The optimum estimator is relaxed according to the iterative quadratic maximum likelihood technique. The remaining parameters are then solved in a linear least squares manner. Theoretical variance expression of the frequency estimate based on high signal-to-noise ratio assumption is also derived. Simulation results show that the proposed algorithm can give optimum estimation performance and is superior to the nonlinear least squares approach.
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In this paper, a recursive Gauss-Newton (RGN) algorithm is first developed for adaptive tracking of the amplitude, frequency and phase of a real sinusoid signal in additive white noise. The derived algorithm is then simplified for... more
In this paper, a recursive Gauss-Newton (RGN) algorithm is first developed for adaptive tracking of the amplitude, frequency and phase of a real sinusoid signal in additive white noise. The derived algorithm is then simplified for computational complexity reduction as well as improved with the use of multiple forgetting factor (MFF) technique to provide a flexible way of keeping track of the parameters with different rates. The effectiveness of the simplified MFF-RGN scheme in sinusoidal parameter tracking is demonstrated via computer simulations.
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In this letter, parameter estimation of a uniformly sampled signal that satisfies the lossy wave equation in Gaussian noise is investigated. By exploiting the linear prediction property of the noise-free signal, a maximum likelihood... more
In this letter, parameter estimation of a uniformly sampled signal that satisfies the lossy wave equation in Gaussian noise is investigated. By exploiting the linear prediction property of the noise-free signal, a maximum likelihood estimator for the parameters is first developed. Relaxation is then applied to yield a simple and accurate algorithm. It is shown that the estimation performance of the proposed method attains Cramér-Rao lower bound.
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This paper describes the LC tank design for low phase noise LC VCO on the selection of passive elements. LC tank based VCO is commonly used for the low phase noise performance in most RF applications. Since quality factor of the LC tank... more
This paper describes the LC tank design for low phase noise LC VCO on the selection of passive elements. LC tank based VCO is commonly used for the low phase noise performance in most RF applications. Since quality factor of the LC tank is mainly dominated by the quality factor of the passive elements (inductor & capacitor) selection, this work presents the passive elements optimization based on the inductor and varactor optimization. Simulated in 65 nm process, higher Q is obtained for large width and minimum number of turns for the inductor and for the varactor design; the PMOS varactor operating in the depletion and accumulation regions allows large tuning range and less parasitic resistance.
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This paper comprises the study and performance analysis of switched capacitor ring voltage controlled oscillator (VCO) which uses the method of controlling capacitance to regulate oscillation frequency. In this paper, three stage ring... more
This paper comprises the study and performance analysis of switched capacitor ring voltage controlled oscillator (VCO) which uses the method of controlling capacitance to regulate oscillation frequency. In this paper, three stage ring oscillator is designed based on added MOS capacitor in the output of each delay cell. 90 nm CMOS process technology has been used in simulation with the supply voltage of 1.8V whereas the variation of control voltage differs from 0V to 0.6V. A linear tuning characteristic has been achieved ranging from 4.52 GHz to 6.02 GHz in pursuit of wireless applications, specifically for IEEE 802.11a standard. The circuit shows very stable output waveform in different parameters with very low power consumption of 0.295 mW. The figure of merit (FoM) is-155.5 dBc/Hz and the phase noise is very reasonable considering the higher oscillation frequency of the circuit.
This paper presents active inductor based VCO design for wireless applications based on analysis of active inductor models (Weng-Kuo Cascode active inductor & Liang Regular Cascode active inductor) with feedback resistor technique.... more
This paper presents active inductor based VCO design for wireless applications based on analysis of active inductor models (Weng-Kuo Cascode active inductor & Liang Regular Cascode active inductor) with feedback resistor technique. Embedment of feedback resistor results in the increment of inductance as well as the quality factor whereas the values are 125.6@2.4GHz (Liang) and 98.7@3.4GHz (Weng-Kuo). The Weng-Kuo active inductor based VCO shows a tuning frequency of 1.765GHz ~2.430GHz (31.7%), while consuming a power of 2.60 mW and phase noise of-84.15 dBc/Hz@1MHz offset. On the other hand, Liang active inductor based VCO shows a frequency range of 1.897GHz ~2.522GHz (28.28%), while consuming a power of 1.40 mW and phase noise of-80.79 dBc/Hz@1MHz offset. Comparing Figure-of-Merit (FoM), power consumption, output power and stability in performance, designed active inductor based VCOs outperform with the state-of-the-art.
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—This paper presents the comparative analysis of active inductor design for high quality factor at high frequency applications on the selection of active inductor topologies. Inductor based circuits are commonly used in integrated... more
—This paper presents the comparative analysis of active inductor design for high quality factor at high frequency applications on the selection of active inductor topologies. Inductor based circuits are commonly used in integrated circuits where the quality factor of the inductor dominates the performance of the designed circuits. Since planner spiral inductor occupies a large area and shows low quality factor, active inductor is a good option to overcome the drawbacks of the spiral inductors. This paper summarizes the analysis and simulation results to select the best active inductor topology for high quality factor at high frequency applications (RF applications). Simulated in Cadence 6.16 environment using the 90 nm CMOS technology, Weng-Kuo active inductor topology shows the higher quality factor as well as high frequency range. Keywords—Active Inductor, RF Integrated Circuits, Voltage-controlled oscillator (VCO), quality factor, LC tank, planner spiral inductor.