With respect to single-electron transistor (SET) technology, it is possible to build neural networks with extreme low power properties. To simulate SET circuits, an electrical model has been represented. In contrast to the prescriptions... more
With respect to single-electron transistor (SET) technology, it is possible to build neural networks with extreme low power properties. To simulate SET circuits, an electrical model has been represented. In contrast to the prescriptions in the so-called Orthodox theory of single-electronics, this model explores the discrete character of the tunnel current and conditions. In this paper a brief description of neural circuitry based tree-island structure was given and verified as a single-electron memory SEM with a well known SET device simulator called SIMON.
This paper presents a simulation of a single-electron transistor "SET" characteristics using MATLAB. SET I-V characteristics presented by developing MATLAB programs. Then we propose a neural circuitry based on single... more
This paper presents a simulation of a single-electron transistor "SET" characteristics using MATLAB. SET I-V characteristics presented by developing MATLAB programs. Then we propose a neural circuitry based on single electron transistors. This kind of neural circuitry can be considered as a single-electron memory "SEM" with four voltages inputs and capacitors connected to a three-island structure extended with an extra
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A simple compact model was proposed to simulate the drain current characteristic for single electron transistor at high temperature, it takes into account all contributions mechanisms; thermionic and tunnel effects. Good agreement was... more
A simple compact model was proposed to simulate the drain current characteristic for single electron transistor at high temperature, it takes into account all contributions mechanisms; thermionic and tunnel effects. Good agreement was reached with experimental results for temperatures up to 430 K. It is valuable for devices with multiple gates and symmetric or asymmetric structures. This result is suitable
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In this paper, we briefly suggest and describe the function of a new memory cell named hybrid MTJ/Ring memory. It is a perfect example of two features combination to obtain new functionalities that are difficult to achieve using either a... more
In this paper, we briefly suggest and describe the function of a new memory cell named hybrid MTJ/Ring memory. It is a perfect example of two features combination to obtain new functionalities that are difficult to achieve using either a pure MTJ or Ring memory cell alone. We present and discuss their characteristics simulated by SIMON Simulator in order to improve the access process for writing and/or reading single electron memory (SEM). Index Terms—Multi-tunnel junction memory, ring memory, MTJ/Ring memory, quantum dot
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We propose a heuristic for the optimal sizing of LC VCO's. The heuristic is an algorithm driven methodology that allows us determining optimal sizes of inductors and channel widths that minimizes the VCO's phase noise while... more
We propose a heuristic for the optimal sizing of LC VCO's. The heuristic is an algorithm driven methodology that allows us determining optimal sizes of inductors and channel widths that minimizes the VCO's phase noise while satisfying fixed constraints (maximum consumed power, occupied area…). The proposed optimization methodology was applied to size a cross-coupled differential voltage controlled oscillator. This latter, designed using AMS 0.35 µm technology, achieves -124.9 dBc/Hz at 1MHz offset from a 2.6 GHz carrier frequency with 8.2mW consumption power and -118.7 dBc/Hz at 1MHz offset from a 5.4 GHz carrier frequency with 8.0mW consumption power.
