2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016
Built-in self-calibration (BiSC) of RF SoCs allows the restoration of a circuit's conformance... more Built-in self-calibration (BiSC) of RF SoCs allows the restoration of a circuit's conformance to its specifications in case of violations due to process variations and device mismatches that are common in nanoscale technologies. A method to optimize BiSC is presented in this paper, by which the number of successfully restored circuits is maximized using the minimum possible number of calibration states. The method is assessed through a case study conducted on a typical RF mixer designed in a 180 nm CMOS technology, and it is shown that yield is doubled by using only five calibration states.
In this paper we propose the design of an easily testable, with respect to path delay faults, n*m... more In this paper we propose the design of an easily testable, with respect to path delay faults, n*m carry-save multiplier (CSM) and give a path selection method such that all the selected paths for testing are Single Path Propagating Hazard Free Robustly Testable (SPP-HFRT). Only three additional test inputs are required while the hardware overhead is very small and the delay overhead negligible.
ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), 2000
In this paper we present the design of a deterministic Test Pattern Generation (TPG) unit which c... more In this paper we present the design of a deterministic Test Pattern Generation (TPG) unit which can be exploited in a Built-In Self-Test (BIST) scheme for memory Neighborhood Pattern Sensitive Fault (NPSF) testing. The proposed TPG generates the required 5-bit Eulerian sequence that is needed for memory Type-1 NPSF testing
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012
ABSTRACT In modern nanotechnologies, the testing of embedded wireless transceivers' RF fr... more ABSTRACT In modern nanotechnologies, the testing of embedded wireless transceivers' RF front-ends is a great concern. The test technique presented in this work is based on dedicated built-in self test (BIST) structures for each building block of the transceiver. These BIST circuits utilize defect-oriented test techniques. Experimental results on a CMOS transceiver design are discussed to accentuate the efficiency of the proposed scheme.
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011
A test technique and a Built-In Self-Test (BIST) circuit to detect catastrophic faults in RF Mixe... more A test technique and a Built-In Self-Test (BIST) circuit to detect catastrophic faults in RF Mixers is presented in this paper. During test application the Mixer is set to operate in homodyne mode and the DC levels generated at its outputs are used as test observables. These test observables are converted to digital signatures, by a simple embedded circuit, and
10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, 2003
Page 1. A NOVEL SCHEME FOR TESTING RADIO FREQUENCY VOLTAGE CONTROLLED OSCILLATORS Lampros Dennenr... more Page 1. A NOVEL SCHEME FOR TESTING RADIO FREQUENCY VOLTAGE CONTROLLED OSCILLATORS Lampros Dennenrzoglou Yiorgos Tsiatouhas Aggeliki Arapoyanni University of Athens Dept. of Informatics & Telecommunications ...
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
This paper presents a cost effective Embedded Test Circuit (ETC) for single ended Low Noise Ampli... more This paper presents a cost effective Embedded Test Circuit (ETC) for single ended Low Noise Amplifiers (LNAs). The ETC operation is based on the observation that the presence of catastrophic faults, like resistive bridgings, shorts and opens, or parametric faults, result in the attenuation of the output voltage amplitude (gain reduction). The ETC along with a single ended LNA have
Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
ABSTRACT In this paper a new built-in self-test (BIST) scheme is proposed suitable for testing di... more ABSTRACT In this paper a new built-in self-test (BIST) scheme is proposed suitable for testing differential voltage controlled ring oscillators. The proposed testing-scheme is capable of detecting single realistic faults of the circuit under test. These faults can be either short or bridging faults between circuit nodes or open faults at the circuit branches. The test result is provided by a digital fail/pass indication signal. Exhaustive simulations have revealed the effectiveness of the proposed technique regarding its fault coverage.
As technology scales down, soft errors, because of single event upsets (SEUs) that affect multipl... more As technology scales down, soft errors, because of single event upsets (SEUs) that affect multiple nodes (through multiple node charge sharing), become a serious concern in nanometre technology integrated circuits. Existing radiation hardening techniques provide partial or no immunity when more than one node are affected. A new latch topology is presented that guarantees soft error tolerance when a single node or any arbitrary combination of node pairs is affected by an SEU. The proposed scheme exploits a positive feedback loop which consists of C-elements. Simulation results validate the efficiency of the new design over existing soft error hardening techniques such as BISER, FERST and TPDICE.
2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
ABSTRACT Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern... more ABSTRACT Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern in CMOS nanometer technologies. In this work, we present pipeline oriented timing error tolerance techniques with a special interest in NBTI related performance degradation. Three scenarios are discussed that provide the required error tolerance in pipeline based designs. Moreover, a new flip-flop is presented, to support two of the above scenarios, which is capable to detect and locally correct timing errors. A main characteristic of the proposed flip-flop is the NBTI resistant error handling operation. Simulation results validate the efficiency of the new design.
Proceedings International Symposium on Quality Electronic Design, 2002
IDDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its ef... more IDDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new IDDQ testing scheme is proposed. This scheme is based on the elimination, during IDDQ testing, of the normal leakage current from the sensing node of the circuit
ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999
Simple to implement, low cost designs in CMOS-domino logic are presented. Novel designs for the t... more Simple to implement, low cost designs in CMOS-domino logic are presented. Novel designs for the two basic gates in domino logic, the AND gate and the OR gate, are presented. These designs need less silicon area and have better performance compared to the standard domino logic designs, while they attain a smaller distribution of the clock signal
Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), 1999
A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circ... more A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circuits is proposed. The BIST scheme is based on a transition detector and is able to detect timing related failures resulting in shorter than expected as well as larger than expected delay faults
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Robust circuit design techniques with respect to soft errors gain importance in the era of very d... more Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an important role towards this direction. In this paper we propose a hierarchical architecture for concurrent soft error detection. This architecture is based on current sensing techniques and provides very low area overhead, small detection times and negligible performance penalty on the functional circuit under check.
2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016
Built-in self-calibration (BiSC) of RF SoCs allows the restoration of a circuit's conformance... more Built-in self-calibration (BiSC) of RF SoCs allows the restoration of a circuit's conformance to its specifications in case of violations due to process variations and device mismatches that are common in nanoscale technologies. A method to optimize BiSC is presented in this paper, by which the number of successfully restored circuits is maximized using the minimum possible number of calibration states. The method is assessed through a case study conducted on a typical RF mixer designed in a 180 nm CMOS technology, and it is shown that yield is doubled by using only five calibration states.
In this paper we propose the design of an easily testable, with respect to path delay faults, n*m... more In this paper we propose the design of an easily testable, with respect to path delay faults, n*m carry-save multiplier (CSM) and give a path selection method such that all the selected paths for testing are Single Path Propagating Hazard Free Robustly Testable (SPP-HFRT). Only three additional test inputs are required while the hardware overhead is very small and the delay overhead negligible.
ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), 2000
In this paper we present the design of a deterministic Test Pattern Generation (TPG) unit which c... more In this paper we present the design of a deterministic Test Pattern Generation (TPG) unit which can be exploited in a Built-In Self-Test (BIST) scheme for memory Neighborhood Pattern Sensitive Fault (NPSF) testing. The proposed TPG generates the required 5-bit Eulerian sequence that is needed for memory Type-1 NPSF testing
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012
ABSTRACT In modern nanotechnologies, the testing of embedded wireless transceivers' RF fr... more ABSTRACT In modern nanotechnologies, the testing of embedded wireless transceivers' RF front-ends is a great concern. The test technique presented in this work is based on dedicated built-in self test (BIST) structures for each building block of the transceiver. These BIST circuits utilize defect-oriented test techniques. Experimental results on a CMOS transceiver design are discussed to accentuate the efficiency of the proposed scheme.
2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011
A test technique and a Built-In Self-Test (BIST) circuit to detect catastrophic faults in RF Mixe... more A test technique and a Built-In Self-Test (BIST) circuit to detect catastrophic faults in RF Mixers is presented in this paper. During test application the Mixer is set to operate in homodyne mode and the DC levels generated at its outputs are used as test observables. These test observables are converted to digital signatures, by a simple embedded circuit, and
10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, 2003
Page 1. A NOVEL SCHEME FOR TESTING RADIO FREQUENCY VOLTAGE CONTROLLED OSCILLATORS Lampros Dennenr... more Page 1. A NOVEL SCHEME FOR TESTING RADIO FREQUENCY VOLTAGE CONTROLLED OSCILLATORS Lampros Dennenrzoglou Yiorgos Tsiatouhas Aggeliki Arapoyanni University of Athens Dept. of Informatics & Telecommunications ...
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
This paper presents a cost effective Embedded Test Circuit (ETC) for single ended Low Noise Ampli... more This paper presents a cost effective Embedded Test Circuit (ETC) for single ended Low Noise Amplifiers (LNAs). The ETC operation is based on the observation that the presence of catastrophic faults, like resistive bridgings, shorts and opens, or parametric faults, result in the attenuation of the output voltage amplitude (gain reduction). The ETC along with a single ended LNA have
Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
ABSTRACT In this paper a new built-in self-test (BIST) scheme is proposed suitable for testing di... more ABSTRACT In this paper a new built-in self-test (BIST) scheme is proposed suitable for testing differential voltage controlled ring oscillators. The proposed testing-scheme is capable of detecting single realistic faults of the circuit under test. These faults can be either short or bridging faults between circuit nodes or open faults at the circuit branches. The test result is provided by a digital fail/pass indication signal. Exhaustive simulations have revealed the effectiveness of the proposed technique regarding its fault coverage.
As technology scales down, soft errors, because of single event upsets (SEUs) that affect multipl... more As technology scales down, soft errors, because of single event upsets (SEUs) that affect multiple nodes (through multiple node charge sharing), become a serious concern in nanometre technology integrated circuits. Existing radiation hardening techniques provide partial or no immunity when more than one node are affected. A new latch topology is presented that guarantees soft error tolerance when a single node or any arbitrary combination of node pairs is affected by an SEU. The proposed scheme exploits a positive feedback loop which consists of C-elements. Simulation results validate the efficiency of the new design over existing soft error hardening techniques such as BISER, FERST and TPDICE.
2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
ABSTRACT Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern... more ABSTRACT Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern in CMOS nanometer technologies. In this work, we present pipeline oriented timing error tolerance techniques with a special interest in NBTI related performance degradation. Three scenarios are discussed that provide the required error tolerance in pipeline based designs. Moreover, a new flip-flop is presented, to support two of the above scenarios, which is capable to detect and locally correct timing errors. A main characteristic of the proposed flip-flop is the NBTI resistant error handling operation. Simulation results validate the efficiency of the new design.
Proceedings International Symposium on Quality Electronic Design, 2002
IDDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its ef... more IDDQ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new IDDQ testing scheme is proposed. This scheme is based on the elimination, during IDDQ testing, of the normal leakage current from the sensing node of the circuit
ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999
Simple to implement, low cost designs in CMOS-domino logic are presented. Novel designs for the t... more Simple to implement, low cost designs in CMOS-domino logic are presented. Novel designs for the two basic gates in domino logic, the AND gate and the OR gate, are presented. These designs need less silicon area and have better performance compared to the standard domino logic designs, while they attain a smaller distribution of the clock signal
Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99), 1999
A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circ... more A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circuits is proposed. The BIST scheme is based on a transition detector and is able to detect timing related failures resulting in shorter than expected as well as larger than expected delay faults
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Robust circuit design techniques with respect to soft errors gain importance in the era of very d... more Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an important role towards this direction. In this paper we propose a hierarchical architecture for concurrent soft error detection. This architecture is based on current sensing techniques and provides very low area overhead, small detection times and negligible performance penalty on the functional circuit under check.
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Papers by Y. Tsiatouhas