A coupled circuit and device simulator is presented for the accurate simulation of phase noise in... more A coupled circuit and device simulator is presented for the accurate simulation of phase noise in RF MEMS VCOs. The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating MEMS capacitors. In addition, the noise from the MEMS capacitor is combined with a nonlinear circuit-level noise analysis to determine the phase noise of the RF MEMS VCO. Simulations of an 800 MHz MEMS VCO implemented in a HP 0.8μm CMOS technology show good agreement with experimentally observed behaviour.
IEEE/ASME Journal of Microelectromechanical Systems, 2005
A new coupled circuit and electrostatic/mechanical simulator (COSMO) is presented for the design ... more A new coupled circuit and electrostatic/mechanical simulator (COSMO) is presented for the design of low phase noise radio frequency (RF) microelectromechanical systems (MEMS) voltage-controlled oscillators (VCOs). The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating MEMS capacitors. In addition, the noise from the MEMS capacitor is combined with a nonlinear circuit-level noise analysis to determine the phase noise of RF MEMS VCO. Simulations of two different MEMS VCO architectures show good agreement with experimentally observed behavior.
In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in ... more In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90 nm CMOS process achieves -63.2 dB THD, 48.8 dB SNR, and 48.6 dB SNDR, while consuming 8 mW from a 1 V supply.
A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DL... more A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency. Test chip fabricated in a 0.13mum CMOS process achieves a DNL below plusmn100fs and plusmn12ps INL and consumes 15mW while operating at 1GHz
We have implemented an optimization technique for the automated design of RF LC CMOS voltage cont... more We have implemented an optimization technique for the automated design of RF LC CMOS voltage controlled oscillators (VCO) with low phase noise given a set of specifications. The electromagnetic solver ASITIC combined with the circuit simulator SpectreRF allows optimization of the VCO circuit parameters and inductor layout. Our approach gives a phase noise improvement of up to 20 dBc/Hz in the flicker noise region and up to 5 dBc/Hz in the thermal noise region. An optimization program for the computer-aided design of on-chip spiral inductors has also been developed. This program allows the designer to obtain the layout of a required inductance value with a maximal quality factor.
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2007
AbstractIn this brief, a systematic design procedure for a second-order all-digital phase-locked... more AbstractIn this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the ...
Abstract A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is pr... more Abstract A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of ...
A coupled circuit and device simulator is presented for the accurate simulation of phase noise in... more A coupled circuit and device simulator is presented for the accurate simulation of phase noise in RF MEMS VCOs. The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating MEMS capacitors. In addition, the noise from the MEMS capacitor is combined with a nonlinear circuit-level noise analysis to determine the phase noise of the RF MEMS VCO. Simulations of an 800 MHz MEMS VCO implemented in a HP 0.8μm CMOS technology show good agreement with experimentally observed behaviour.
IEEE/ASME Journal of Microelectromechanical Systems, 2005
A new coupled circuit and electrostatic/mechanical simulator (COSMO) is presented for the design ... more A new coupled circuit and electrostatic/mechanical simulator (COSMO) is presented for the design of low phase noise radio frequency (RF) microelectromechanical systems (MEMS) voltage-controlled oscillators (VCOs). The numerical solution of device level equations is used to accurately compute the capacitance of a MEMS capacitor. This coupled with a circuit simulator facilitates the simulation of circuits incorporating MEMS capacitors. In addition, the noise from the MEMS capacitor is combined with a nonlinear circuit-level noise analysis to determine the phase noise of RF MEMS VCO. Simulations of two different MEMS VCO architectures show good agreement with experimentally observed behavior.
In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in ... more In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90 nm CMOS process achieves -63.2 dB THD, 48.8 dB SNR, and 48.6 dB SNDR, while consuming 8 mW from a 1 V supply.
A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DL... more A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency. Test chip fabricated in a 0.13mum CMOS process achieves a DNL below plusmn100fs and plusmn12ps INL and consumes 15mW while operating at 1GHz
We have implemented an optimization technique for the automated design of RF LC CMOS voltage cont... more We have implemented an optimization technique for the automated design of RF LC CMOS voltage controlled oscillators (VCO) with low phase noise given a set of specifications. The electromagnetic solver ASITIC combined with the circuit simulator SpectreRF allows optimization of the VCO circuit parameters and inductor layout. Our approach gives a phase noise improvement of up to 20 dBc/Hz in the flicker noise region and up to 5 dBc/Hz in the thermal noise region. An optimization program for the computer-aided design of on-chip spiral inductors has also been developed. This program allows the designer to obtain the layout of a required inductance value with a maximal quality factor.
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2007
AbstractIn this brief, a systematic design procedure for a second-order all-digital phase-locked... more AbstractIn this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the ...
Abstract A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is pr... more Abstract A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of ...
Uploads
Papers by Volodymyr Kratyuk