—This paper proposes a novel single-well VCO in PLL architecture targeting ZigBee (ZB) and Blueto... more —This paper proposes a novel single-well VCO in PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs PMOS based charge recycling technique in Voltage Controlled Oscillator (VCO) and a Current Mode Logic (CML) divider for I-Q generation in single-well CMOS. An efficient, low current, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The VCO-CML cell gives phase noise of-147 dBc/Hz at 1 MHz offset. PLL consumes 1.2mW of power at 1.2V supply with a settling time less than 45µs and core area is 743µm x 416µm using UMC 0.18µm CMOS Mixed Mode Technology.
—This paper proposes a PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It emp... more —This paper proposes a PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs a single-well, direct back-gated Quadrature Voltage Controlled Oscillator (QVCO). An efficient, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The QVCO gives phase noise of-110 dBc/Hz at 1 MHz offset. PLL consumes 450µW of power at 0.8 V supply with a settling time less than 25µs and core area is 705 µm x 510 µm at UMC 0.18 µm CMOS Mixed Mode Technology. PLL is successfully tested with the energy harvesting circuit.
—This paper proposes a novel single-well VCO in PLL architecture targeting ZigBee (ZB) and Blueto... more —This paper proposes a novel single-well VCO in PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs PMOS based charge recycling technique in Voltage Controlled Oscillator (VCO) and a Current Mode Logic (CML) divider for I-Q generation in single-well CMOS. An efficient, low current, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The VCO-CML cell gives phase noise of-147 dBc/Hz at 1 MHz offset. PLL consumes 1.2mW of power at 1.2V supply with a settling time less than 45µs and core area is 743µm x 416µm using UMC 0.18µm CMOS Mixed Mode Technology.
—This paper proposes a PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It emp... more —This paper proposes a PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs a single-well, direct back-gated Quadrature Voltage Controlled Oscillator (QVCO). An efficient, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The QVCO gives phase noise of-110 dBc/Hz at 1 MHz offset. PLL consumes 450µW of power at 0.8 V supply with a settling time less than 25µs and core area is 705 µm x 510 µm at UMC 0.18 µm CMOS Mixed Mode Technology. PLL is successfully tested with the energy harvesting circuit.
Uploads
Papers by Sesha Sairam