Igor Markov
University of Michigan, EECS, Faculty Member
ABSTRACT This panel focuses on how new Web-based frameworks can enable academic research and development in VLSI CAD. Open-source initiatives, portals for research communities or for the EDA community at large, algorithm benchmarking... more
ABSTRACT This panel focuses on how new Web-based frameworks can enable academic research and development in VLSI CAD. Open-source initiatives, portals for research communities or for the EDA community at large, algorithm benchmarking support, etc. are a few of the possibilities. Each of the three panelists will describe the current status of efforts toward building new Web-based infrastructure for CAD research. The approaches and “mission statements” illustrate the literally unbounded potential for such frameworks to transform how CAD R&D is performed.
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Research Interests: Computer Science, Software Engineering, Design, Visualization, Open Source Software, and 13 moreOpen Source, Infrastructure Development, Software, EDA, Timing, Experimentation, Retrofitting, Placement, Physical Design, Open Source Software Development, Database, Static timing analysis, and Early experience
Separate optimizations of logic and layout have been thoroughly studied in the past and are well documented for common bench- marks. However, to be competitive, modern circuit optimizations must use physical and logic information... more
Separate optimizations of logic and layout have been thoroughly studied in the past and are well documented for common bench- marks. However, to be competitive, modern circuit optimizations must use physical and logic information simultaneously. In this work, we propose new algorithms for rewiring and rebuffer- ing — a post-placement optimization that reconnects pins of a given netlist without changing
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On-chip clock networks are remarkable in their impact on the performance and power of synchronous circuits, in their susceptibility to adverse effects of semiconductor technology scaling, as well as in their strong potential for... more
On-chip clock networks are remarkable in their impact on the performance and power of synchronous circuits, in their susceptibility to adverse effects of semiconductor technology scaling, as well as in their strong potential for improvement through better CAD algorithms and tools. Existing literature is rich in ideas and techniques but performs large-scale optimization using analytical models that lost accuracy at recent technology nodes and have rarely been validated by realistic SPICE simulations on large industry designs. Our work offers a methodology for SPICE-accurate optimization of clock networks, coordinated to satisfy slew constraints and achieve best tradeoffs between skew, insertion delay, power, as well as tolerance to variations. Our implementation, called Contango, is evaluated on 45 nm benchmarks from IBM Research and Texas Instruments with up to 50 K sinks. It outperforms all published results in terms of skew and shows superior scalability.
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Research Interests: Computer Science, Computer Engineering, Computer Hardware, Digital Circuits, Digital Electronics, and 10 moreRestructuring, High performance, Design optimization, Logic Synthesis, Logic Gate, Interconnection, Logic Optimization, Electrical And Electronic Engineering, Delay Estimation, and Logic family
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Global interconnects are a bottleneck in today's high-performance deep sub-micron designs. In this paper, we propose a modification to the top-down min-cut placement algorithm to reduce the number of global interconnects. Our method... more
Global interconnects are a bottleneck in today's high-performance deep sub-micron designs. In this paper, we propose a modification to the top-down min-cut placement algorithm to reduce the number of global interconnects. Our method is generic and does not involve any timing analysis during or prior to placement. In essence, we skew the netlength distribution produced by a min-cut placer so as to reduce the number of long nets, with minimal impact on the overall wirelength. Empirically this approach has a negligible ...
In analytical placement, one seeks locations of circuit modules that optimize an objective function, but allows module overlaps. Our work introduces a novel minimization of maximal path delay that improves upon previously known algorithms... more
In analytical placement, one seeks locations of circuit modules that optimize an objective function, but allows module overlaps. Our work introduces a novel minimization of maximal path delay that improves upon previously known algorithms for timing-driven placement. Our placement algorithms have provable properties and are fast in practice.
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In this work, we study multiobjective thermal-aware floorplanning in the fixed-outline context. Our baseline implementation demonstrates a 14% average interconnect improvement over Parquet for ami49, and can additionally optimize peak... more
In this work, we study multiobjective thermal-aware floorplanning in the fixed-outline context. Our baseline implementation demonstrates a 14% average interconnect improvement over Parquet for ami49, and can additionally optimize peak on-chip temperature. To circumvent the expense of Compact Thermal Models, we develop a novel approach to power-density aware floorplanning, but rigorously evaluate final layouts using a standard methodology based on the Hotspot tool. With these techniques, our ...
We propose two new algorithms for rewiring: a postplacement optimization that reconnects pins of a given netlist without changing the logic function and gate locations. In the first algorithm, we extract small subcircuits consisting of... more
We propose two new algorithms for rewiring: a postplacement optimization that reconnects pins of a given netlist without changing the logic function and gate locations. In the first algorithm, we extract small subcircuits consisting of several gates from the design and reconnect pins according to the symmetries of the subcircuits. To enhance the power of symmetry detection, we also propose a graph-based symmetry detector that can identify permutational and phase-shift symmetries on multiple input and output wires, as well as hybrid symmetries, creating abundant opportunities for rewiring. Our second algorithm, called long-range rewiring, is based on reconnecting equivalent pins and can augment the first approach for further optimization. We apply our techniques for wirelength optimization and observe that they provide wirelength reduction comparable to that achieved by detailed placement.
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In this work, we propose a new and efficient approach to the floorplan repair problem, where violated design constraints are satisfied by applying small changes to an existing rough floorplan. Such a floorplan can be produced by a human... more
In this work, we propose a new and efficient approach to the floorplan repair problem, where violated design constraints are satisfied by applying small changes to an existing rough floorplan. Such a floorplan can be produced by a human designer, a scalable placement algorithm, or result from engineering adjustments to an existing floorplan. In such cases, overlapping modules must be separated, and others may need to be repositioned to satisfy additional requirements. Our algorithmic framework uses an expressive graph-based encoding of constraints which can reflect fixed-outline, region, proximity and alignment constraints. By tracking the implications of existing constraints, we resolve violations by imposing gradual modifications to the floorplan, in an attempt to preserve the characteristics of its initial design. Empirically, our approach is effective at removing overlaps and repairing violations that may occur when design constraints are acquired and imposed dynamically.
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We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the original non-convex problem into\more convex"sub-problems.... more
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the original non-convex problem into\more convex"sub-problems. It generalizes the recent SimPL, SimPLR and Ripple algo- rithms and extends them. Empirically, ComPLx outper- forms all published placers in runtime and performance on ISPD 2005 and 2006 benchmarks.
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ABSTRACT This panel focuses on how new Web-based frameworks can enable academic research and development in VLSI CAD. Open-source initiatives, portals for research communities or for the EDA community at large, algorithm benchmarking... more
ABSTRACT This panel focuses on how new Web-based frameworks can enable academic research and development in VLSI CAD. Open-source initiatives, portals for research communities or for the EDA community at large, algorithm benchmarking support, etc. are a few of the possibilities. Each of the three panelists will describe the current status of efforts toward building new Web-based infrastructure for CAD research. The approaches and “mission statements” illustrate the literally unbounded potential for such frameworks to transform how CAD R&D is performed.
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In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as “whitespace.” This is done for a variety of reasons including the need for subsequent buffer insertion, as a... more
In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as “whitespace.” This is done for a variety of reasons including the need for subsequent buffer insertion, as a means to ensure routability, signal integrity, and low coupling capacitance between wires, and to improve yield through DFM optimizations. To this end, layout constraints often require a certain minimum fraction of whitespace in each region of the chip. Our work introduces several techniques for allocation of whitespace in global, detail, and incremental placement. Our experiments show how to efficiently improve wirelength by reallocating whitespace in legal placements at the large scale. Additionally, for the first time in the literature, we empirically demonstrate high-precision control of whitespace in designs with macros and obstacles. Our techniques consistently improve the quality of whitespace allocation of top-down as well as analytical plac...
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Research Interests: Engineering, Computer Science, Computer Hardware, High Level Synthesis, VERY LARGE SCALE INTEGRATED CIRCUITS, and 10 moreVery Large Scale Integration, System Reliability, Algorithm Design, Macro, Flexibility in engineering design, Physical Design, Integrated Circuit, Interconnection, Electrical And Electronic Engineering, and Engineering Change Order
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Research Interests: Engineering, Computer Science, Computer Architecture, Intellectual Property, System Integration, and 14 moreComputer Hardware, New Technology, Reuse, IP networks, Chip, Three Dimensional, Integrated Circuit, Logic Gate, Through-silicon via, Design Reuse, Embedded System, Electrical And Electronic Engineering, Logic circuits, and High risk
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The technique of using balanced min-cut partitioning in placement was presented by Breuer in 1977 [7]. Such min-cut placers use scalable and extensible divide-and-conquer algorithmic framework and tend to produce routable placements [9].... more
The technique of using balanced min-cut partitioning in placement was presented by Breuer in 1977 [7]. Such min-cut placers use scalable and extensible divide-and-conquer algorithmic framework and tend to produce routable placements [9]. Recent work offers extensions to block placement and large-scale mixed-size placement [15, 18, 31], and robust incremental placement [33]. Over the years partitioning-based placement has seen many revisions and enhancements, but the underlying framework (illustrated in Figure 1) ...
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis and timing-driven placement end up hurting the final result, often by neglecting important physical... more
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis and timing-driven placement end up hurting the final result, often by neglecting important physical aspects of the layout, such as long wires or routing congestion. Our work defines and explores the concepts of physical safeness and logical soundness, and empirically evaluates the effects of physical safeness on route length, via count and timing. In addition, we propose a new physically safe and ...
Over the past few decades, several powerful placement algorithms have been used successfully in performing VLSI placement. With the increasing complexity of the VLSI chips, there is no clear dominant placement paradigm today. This work... more
Over the past few decades, several powerful placement algorithms have been used successfully in performing VLSI placement. With the increasing complexity of the VLSI chips, there is no clear dominant placement paradigm today. This work attempts to explore hybrid algorithms for large-scale VLSI placement. Our work aims to evaluate existing placement algorithms, estimate the ease of their reuse, and identify their sensitivities and limitations. We study particular aspects of large-scale placement and particular types of ...
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While recent literature on circuit layout addresses large-scale standard-cell placement, the authors typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of... more
While recent literature on circuit layout addresses large-scale standard-cell placement, the authors typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of placeable objects. Therefore we combine floorplanning techniques with placement techniques to solve the more general placement problem. Our work shows how to place macros consistently with large numbers of small standard cells. Proposed techniques can also be used to guide circuit designers who prefer to place macros by hand.We address the computational difficulty of layout problems involving large macros and numerous small logic cells at the same time. Proposed algorithms are evaluated in the context of wirelength minimization because a computational method that is not scalable in optimizing wirelength is unlikely to be successful for more complex objectives (congestion, delay, power, etc.)We propose several different design flows to pla...