Floorplanning

In today’s VLSI field the exponentially increasing factor of integration takes the techniques of chip designing to be more cared about both switch level (eg. device, logic gate design, etc.) and chip level (eg. pad design, floorplanning, routing, etc.) as size of chip is continually decreasing and power consumption challenge is getting tougher. To design a complete & successful functional chip, pad frame design and floorplanning are also challenging. This study is an attempt to present a VLSI design of pad frame with less power consuming I/O architecture with an efficient way of floorplanning which includes block placement, global routing, detail routing. MAGIC is used as layout designing CAD tool to design the pad frame as it is the easiest and worldwide CAD tool for VLSI layout design, and for simulation purpose PSpice is used. This study presents details of the key research work, results, techniques and efficient way of pad frame design as well as floorplanning.

In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its port. In addition, we pr opose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation,in

ABSTRAK
Dunia hiburan yang terdiri dari berbagai aspek merupakan salah satu kebutuhan manusia yang juga merupakan salah satu peluang bisnis di sektor jasa dengan pasar potensial yang tidak pernah berhenti. Dunia Cinema yang bersaing dengan dunia cyber dengan pelanggan yang beragam, diperlukan sebuah sarana dengan interior unik, dan fasilitas yang mendukung serta kenyamanan dalam aspek interior. Sudah di ketahui bahwa Interior sebuah usaha juga merupakan aspek penting akan keberhasilan dalam tiap bisnis usaha yang dilakukan sehingga memberikan suatu ciri khas tersendiri yang berkesan.
Konsep Futuristik yang akan diaplikasikan pada interior Cinema Lounge ini, dimaksud akan menjadi suatu ciri khas dan daya tarik tersendiri serta pengguna dapat merasa nyaman saat menggunakan fasilitas yang di sajikan, khususnya pada zaman sekarang apalagi dengan pasar kota Medan. Bahan yang merupakan perpaduan lantai concrete dengan permukaan furniture yang mengkilap, penggunaan kaca dan aluminium memberikan suasana yang sangat futuristik, serta membuat para pengguna jasa merasa bahwa terbawa ke tempat lain sebelum menikmati sajian film pilihannya. Konsep Futuristik merupakan sebuah konsep yang dimana para designer interior dapat dengan bebas berekspresi di dalam ruangan tersebut. Penelitian ini merupakan penelitian kualitatif dengan desain deskriptif.
Berdasarkan data yang diperoleh di lapangan serta analisis yang telah dilakukan diketahui bahwa 1) Desainer Interior perlu dilibatkan dalam pengembangan Bisnis Cinema. 2) memberikan masukan secara keilmuan kepada pihak pengelola, agar dari segi Desain Interior lebih baik dengan memperhatikan analisa ilmu interior dan memadukan usur Futuristik sebagai salah satu wadah untuk memberikan nuansa dan konsep desain yang berbeda, serta 3) meningkatkan daya tarik dan penggunaan jasa lounge pada Cinema tersebut.

Kata kunci: Cinema lounge, Gaya desain Futuristik

ABSTRACT
The world of entertainment consisting of various aspects of human needs which is also one of the business opportunities in the service sector with a potential market that never stops. Around the cinema world which is competing with the cyber world with diverse customers, needed an instrument with a unique interior, and facilities that support and comfort in the interior aspect. Already known that the interior in business is also an important aspect of success in any business venture undertaken so as to provide a memorable distinctive characteristics.
Futuristic concept which will be applied to the interior's Cinema Lounge, is going to be a characteristic and distinctive charm and users can feel comfortable when using the facilities at present, particularly in the market today especially with the city of Medan. Material which is a combination of concrete floors with furniture shiny surfaces, the use of glass and aluminum to provide an atmosphere that is very futuristic, and make service users felt that carried to another place before enjoying a movie offerings choice. Futuristic concept is a concept where interior designers can freely express in the room. This research is a qualitative descriptive design.
Based on the field data and analysis has been made known that 1) Interior Designers need to be involved in the development of Business Cinema. 2) provide input  to the manager, so in terms of Interior Design better with attention to the analysis of the science of interior and blends the Futuristic style to give a different sense of design concept, and 3) increase the attractiveness and use of the service lounge on the Cinema.

Keywords: Cinema lounge, Futuristic design style

A methodology is presented for the physical design automation of array-type analog blocks such as encountered in high-speed data converters and other analog circuits. The approach takes into consideration typical analog constraints and offers full flexibility. A three-step procedure (floorplanning, symbolic routing, and technology mapping), of which the last two steps have been automated in a tool called Mondriaan, solves the layout synthesis problem in a fast and technology-independent way. A set of bus and tree device generators complements the tool set. Industrial-strength examples prove that the proposed solution speeds up the generation of high-quality analog layouts significantly

Partial reconfiguration (PR) is gaining more attention from the research community because of its flexibility in dynamically changing some parts of the system at runtime. However , the current PR tools need the designer's involvement in manually specifying the shapes and locations for the PR regions (PRRs). It requires not only deep knowledge of the FPGA device, the system architecture, but also many trial-and-error attempts to find the best-possible floorplan. Therefore, many research works have been conducted to propose automatic floorplanners for PR systems. However, one of the most significant limitations of those works is that they only consider the PRRs and ignore all other static modules. In this paper, we propose a novel PR floorplanner called PRFloor. It takes into account all components in the system. The main ideas behind PRFloor are the unique re-cursive pseudo-bipartitioning heuristic using a new, simple, yet effective Nonlinear Integer Programming-based biparti-tioner. The PRFloor performs very well in the experiments with various synthetic PR system setups with up to 130 modules, 24 PRRs and 85% of the FPGA resource. The average maximum clock frequency obtained for the actual PR systems implemented using PRFloor is even 3% higher than the similar systems without PR capability.

As demonstrated by the ISPD 2005 and 2006 placement contests, automated layout of modern systems-on-chip (SoCs) is very different from traditional sea-of-gates layout, both in scale and sophistication [1]. Such integrated circuits (ICs) may contain tens of millions of logic gates, ...

D die-stacked chips can alleviate the penalties imposed by long wires within micro- processor circuits. Many recent studies have attempted to partition each microprocessor structure across three dimensions to reduce their access times. In this paper, we implement each microprocessor structure on a single 2D die and leverage 3D to reduce the lengths of wires that communicate data between microprocessor structures within a single core. We begin with a criticality analysis of inter-structure wire delays and show that for most tra- ditional simple superscalar cores, 2D o orplans are already very ecien t at minimizing critical wire delays. For an aggressive wire-constrained clustered superscalar architecture, an exploration of the design space reveals that 3D can yield higher benet. However, this benet may be negated by the higher power density and temperature entailed by 3D in- tegration. Overall, we report a negative result and argue against leveraging 3D for higher ILP.

In this paper we consider architectural layout problem that seeks to determine the layout of Units based on lighting, heating, available sizes and other objectives and constraints. For a conceptual design of architectural layout we present an approach based on evolutionary search method known as the genetic algorithms (GAs). However, the rate of convergence of GAs is often not good enough at their current stage. For this reason, the improved genetic algorithm is proposed. We have analysed and compared the performance of standard and improved genetic algorithm for architectural layout problem solutions and presented the results of performance.

From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms. Copyright (c) 2013 John Wiley & Sons, Ltd.

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http://onlinelibrary.wiley.com/doi/10.1002/cta.1939/abstract 
http://repository.um.edu.my/29500/1/Cost%20Reduction%20in%20Bottom-up%20Hierarchical-based%20VLSI%20Floorplanning%20Designs.pdf

A massively parallel implementation of an RC4 key search engine on an FPGA is described. The design employs parallelism at the logic level to perform many operations per cycle, uses on-chip memories to achieve very high memory bandwidth, floorplanning to reduce routing delays and multiple decryption units to achieve further parallelism. A total of 96 RC4 decryption engines were integrated

Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floor-planner. Our contributions include: (1) a novel multi-objective formulation to consider the thermal and performance constraints in the optimization approach; (2) an efficient Mixed Integer Linear Programming (MILP) representation of the floorplanning model; and (3) a smooth integration of the MILP model with an accurate thermal modelling of the architecture. The experimental work is conducted for two realistic many-core single-chip architectures: an homogeneous system resembling Intel's SCC, and an improved heterogeneous setup. The results show promising improvements of the mean, peak temperature and the thermal gradient, with a reduced overhead in the wire length of the system.