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Research Interests: Applied Mathematics, Combinatorial Optimization, Modeling, Pure Mathematics, Comparative Study, and 15 moreOptimization Problem, Non Linear Programming, System on Chip, Global Optimization, Dimensioning, Circuit Design, Convex Programming, Overlap, System on a Chip, Physical Design, Numerical Analysis and Computational Mathematics, Height, Aspect Ratio, Global Optimum, and Nonlinear Optimization
ABSTRACT We describe an improved technique for handling large numbers of cutting planes when using an interior-point method for the solution of linear and semi-definite programming relaxations of combinatorial optimization problems. The... more
ABSTRACT We describe an improved technique for handling large numbers of cutting planes when using an interior-point method for the solution of linear and semi-definite programming relaxations of combinatorial optimization problems. The approach combines an infeasible primal-dual interior-point algorithm with a cutting-plane scheme that does not solve successive relaxations to optimality, but adds and removes cuts at intermediate iterates based on indicators for cut violation and feasibility of the associated slacks. The slack variables of added cuts are initialized using a recently proposed interior-point warm-start technique that relaxes the interiority condition on the original primal-dual variables and enables a restart from the current iterate without additional centring or correction steps. Our computational tests on relaxations of the maximum-cut and single-row facility-layout problem demonstrate that this new scheme is robust for both unconstrained and constrained binary quadratic problems and that its performance is superior to solving only the final relaxation with all relevant cuts known in advance.
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ABSTRACT This paper describes a fast greedy clustering algorithm for circuit partitioning. The algorithm is used to generate a good initial partitioning, then a module interchange approach is used to improve the initial partitioning. The... more
ABSTRACT This paper describes a fast greedy clustering algorithm for circuit partitioning. The algorithm is used to generate a good initial partitioning, then a module interchange approach is used to improve the initial partitioning. The proposed algorithm is tested against three well known algorithms namely, simulated annealing, Tabu search approach, and module interchange algorithm alone using some benchmark netlist partitioning problems (between 300 to 3000 nets and modules each). Test results show that the proposed algorithm yields results comparable to that of the other approaches with a faster execution time
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... II. Optimal Power Flow and System Modeling The objective of the economic dispatch problem is to minimize the instantaneous operating costs in a trans-mission system. ... min. ctx 5 st Ax = b; x 0 by nding the solution to the dual... more
... II. Optimal Power Flow and System Modeling The objective of the economic dispatch problem is to minimize the instantaneous operating costs in a trans-mission system. ... min. ctx 5 st Ax = b; x 0 by nding the solution to the dual problem: max. bty 6 st ATx c; r 0 ...
Research Interests: Economics, Power Systems, Linear Programming, Interior Point Methods, Computer Languages, and 10 moreOscillations, Optimal Power Flow, Sequential Analysis, Numerical Stability, Load Flow, Digital System Testing, Cost Function, Power flow, Electrical and Computer Engineering, and Quadratic Programming
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... Furthermore, the SRLP is closely related to the linear ordering problem, which also has a number of practical applications, see eg [5, 6, 13]. The SRLP was first studied by Simmons [14] who proposed a branch-and-bound algorithm. ...... more
... Furthermore, the SRLP is closely related to the linear ordering problem, which also has a number of practical applications, see eg [5, 6, 13]. The SRLP was first studied by Simmons [14] who proposed a branch-and-bound algorithm. ... 278 Miguel F. Anjos, Anthony Vannelli ...
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Cell placement can be performed using a combination of mathematical programming, graph partitioning and iterative improvement techniques. Mathematical programming provides the relative positions of cells throughout the placement area... more
Cell placement can be performed using a combination of mathematical programming, graph partitioning and iterative improvement techniques. Mathematical programming provides the relative positions of cells throughout the placement area while ignoring several placement restrictions. We describe quadratic and linear program formulations for finding relative cell positions. Moreover, we demonstrate that both formulations can be solved using an interior point method. Numerical results are presented to demonstrate the effectiveness of the formulations and the solution methodology
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Ana/ytic placement methods that simultaneously minimize wire length and spread cells are receiving renewed attention from both academia and industiy In this paper we describe the implementation details of a force-directed placer: FDP.... more
Ana/ytic placement methods that simultaneously minimize wire length and spread cells are receiving renewed attention from both academia and industiy In this paper we describe the implementation details of a force-directed placer: FDP. Specifically, we provide (I) a description of eficient force computation for spreading cells, (2) an illustration of numer- ical instability in these methods and a meam by
ABSTRACT-Due to the rapid growth of technologies, Systems-on-Chip (SoC) have started to become a key is-sue in today's electronic industry. In deep submicron designs, the interconnect is responsible for more than 90 percent of the... more
ABSTRACT-Due to the rapid growth of technologies, Systems-on-Chip (SoC) have started to become a key is-sue in today's electronic industry. In deep submicron designs, the interconnect is responsible for more than 90 percent of the signal delay in a chip. This paper presents ...
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Abstract A comparison of Nash-Cournot equilibria using DC and AC approximations of the transmission system is presented in this paper. The goal of doing this comparison is to identify the impact of reactive power and voltage-related... more
Abstract A comparison of Nash-Cournot equilibria using DC and AC approximations of the transmission system is presented in this paper. The goal of doing this comparison is to identify the impact of reactive power and voltage-related issues on Nash equilibria. Following the ...
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ABSTRACT We describe an improved technique for handling large numbers of cutting planes when using an interior-point method for the solution of linear and semi-definite programming relaxations of combinatorial optimization problems. The... more
ABSTRACT We describe an improved technique for handling large numbers of cutting planes when using an interior-point method for the solution of linear and semi-definite programming relaxations of combinatorial optimization problems. The approach combines an infeasible primal-dual interior-point algorithm with a cutting-plane scheme that does not solve successive relaxations to optimality, but adds and removes cuts at intermediate iterates based on indicators for cut violation and feasibility of the associated slacks. The slack variables of added cuts are initialized using a recently proposed interior-point warm-start technique that relaxes the interiority condition on the original primal-dual variables and enables a restart from the current iterate without additional centring or correction steps. Our computational tests on relaxations of the maximum-cut and single-row facility-layout problem demonstrate that this new scheme is robust for both unconstrained and constrained binary quadratic problems and that its performance is superior to solving only the final relaxation with all relevant cuts known in advance.
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The design of dynamic Label-Switched Paths (LSP’s) in MultiProtocol Label Switched (MPLS) networks is an NP-hard optimization problem. An LSP is a logical path between two nodes in the network. This path has a pre-reserved amount of... more
The design of dynamic Label-Switched Paths (LSP’s) in MultiProtocol Label Switched (MPLS) networks is an NP-hard optimization problem. An LSP is a logical path between two nodes in the network. This path has a pre-reserved amount of bandwidth that defines its size. The LSP design problem consists of determining the number of these logical links and configuring the physical path
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Research Interests: Applied Mathematics, Combinatorial Optimization, Modeling, Pure Mathematics, Comparative Study, and 15 moreOptimization Problem, Non Linear Programming, System on Chip, Global Optimization, Dimensioning, Circuit Design, Convex Programming, Overlap, System on a Chip, Physical Design, Numerical Analysis and Computational Mathematics, Height, Aspect Ratio, Global Optimum, and Nonlinear Optimization
... quadratic programming, interior point method, preconditioned iterative solvers 1. INTRODUCTION In the design of an integrated circuit, circuit layout represents the step where a physical realization of the circuit is obtained from its... more
... quadratic programming, interior point method, preconditioned iterative solvers 1. INTRODUCTION In the design of an integrated circuit, circuit layout represents the step where a physical realization of the circuit is obtained from its functional description (Hu and Kuh, 1985). ...
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In this paper, oligopolistic competition in a centralized power market is characterized by a multi-leader single-follower game, and formulated as a nonlinear programming (NLP) problem. An ac network is used to represent the transmission... more
In this paper, oligopolistic competition in a centralized power market is characterized by a multi-leader single-follower game, and formulated as a nonlinear programming (NLP) problem. An ac network is used to represent the transmission system and is modeled using rectangular coordinates. The follower is composed of a set of competitive suppliers, demands, and the system operator, while the leaders are the dominant suppliers. The ac approach allows one to capture the strategic behavior of suppliers regarding not only active but also reactive power. In addition, the impact of voltage and apparent power flow constraints can be analyzed. Different case studies are presented using a three-node system to highlight the features of the formulation. Results on a 14-node system are also presented
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—With the ever increasing die sizes and the accompanied increase in the average global interconnect length, delay-optimal-routing and buffer-insertion techniques are significantly straining the power budget of modern ICs. To mitigate the... more
—With the ever increasing die sizes and the accompanied increase in the average global interconnect length, delay-optimal-routing and buffer-insertion techniques are significantly straining the power budget of modern ICs. To mitigate the impact of the power consumed by the interconnects and buffers, a power-efficient multipin routing technique is proposed in this paper. The problem is based on a graph representation of the routing possibilities, with the objective of identifying the minimum power path between the interconnect source and set of sinks. The technique is tested by applying it to the International Symposium on Physical Design and IBM benchmarks to verify the accuracy, complexity, and solution quality. Results obtained indicate that an average power saving as high as 32% for the 130-nm technology is achieved with no impact on the maximum chip frequency.