Ieee Transactions on Components Packaging and Manufacturing Technology, Apr 1, 2015
We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networ... more We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networks (PDNs) for hierarchical on-die simulation and interconnect noise analysis. This paper compares the quality of power delivery in 3-D stacking scenarios for three distinct chip stacking topologies: 1) face-to-back (F2B); 2) face-to-face (F2F); and 3) back-to-back (B2B). Quantitatively, this paper compared the impedance noise level between the three stacking topologies and found the PDN impedance noise of F2F chip stacking to be relatively lower than F2B and B2B chip stacking topologies. A power delivery impedance below 1 Ω for F2F chip stacking topology was possible up to 2 GHz. However, for F2B and B2B chip stacking, the PDN impedance could not get beyond sub-1 Ω. The impedance was simulated between 0.1 and 20 GHz. Among power grid and power and ground TSV models presented in this paper, we also present and implemented a metal-insulator-metal capacitor model written as a complex impedance equation. With capacitor dimensions similar to the unit cell gird size (200 μm × 200 μm), the capacitance density (per unit area) ranged from 0.062 pF/μm2 to 5.325 fF/μm2.
Storage and Retrieval For Image and Video Databases, 1998
Reconfigurable machines have recently been used as co- processors to accelerate the execution of ... more Reconfigurable machines have recently been used as co- processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: (1) the small on-chip memory which results in slower execution time, and (2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory access problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implemented multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X faster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710), 2003
A unified method is presented for layout and package design implemented within a commercial desig... more A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.
ABSTRACT Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many ... more ABSTRACT Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many challenges. In this work, we present new techniques for realizing highly adaptive and reliable clock distribution for 3D ICs. Firstly, an efficient clock distribution topology without need of balanced H-tree is proposed. Secondly, a robust tunable-delay-buffer (TDB) circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry. Moreover, a design optimization flow is constructed for improving the adaptive clock design based on the thermal profiles. Experiment results show that the clock skews are significantly reduced using the proposed techniques.
This paper presents some results from phase-1 research into developing a beam steerer based on mi... more This paper presents some results from phase-1 research into developing a beam steerer based on micro-mechanical diffractive elements. The position of these elements is electrostatically controlled, to allow dynamic programming of a 2D phase function. Feasibility prototypes were constructed in the MUMPs polysilicon surface micromachine process.
A new proposal of applying surrogate-modeling in input-output buffer information specification (I... more A new proposal of applying surrogate-modeling in input-output buffer information specification (IBIS) is presented. It saves the IBIS data storage resource, extends the model utility to various process-voltage-temperature (PVT) simulations and eliminates the data interpolation deviations.
In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses an... more In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its port. In addition, we pr opose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation,in
Ieee Transactions on Components Packaging and Manufacturing Technology, Apr 1, 2015
We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networ... more We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networks (PDNs) for hierarchical on-die simulation and interconnect noise analysis. This paper compares the quality of power delivery in 3-D stacking scenarios for three distinct chip stacking topologies: 1) face-to-back (F2B); 2) face-to-face (F2F); and 3) back-to-back (B2B). Quantitatively, this paper compared the impedance noise level between the three stacking topologies and found the PDN impedance noise of F2F chip stacking to be relatively lower than F2B and B2B chip stacking topologies. A power delivery impedance below 1 Ω for F2F chip stacking topology was possible up to 2 GHz. However, for F2B and B2B chip stacking, the PDN impedance could not get beyond sub-1 Ω. The impedance was simulated between 0.1 and 20 GHz. Among power grid and power and ground TSV models presented in this paper, we also present and implemented a metal-insulator-metal capacitor model written as a complex impedance equation. With capacitor dimensions similar to the unit cell gird size (200 μm × 200 μm), the capacitance density (per unit area) ranged from 0.062 pF/μm2 to 5.325 fF/μm2.
Storage and Retrieval For Image and Video Databases, 1998
Reconfigurable machines have recently been used as co- processors to accelerate the execution of ... more Reconfigurable machines have recently been used as co- processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: (1) the small on-chip memory which results in slower execution time, and (2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory access problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implemented multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X faster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710), 2003
A unified method is presented for layout and package design implemented within a commercial desig... more A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.
ABSTRACT Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many ... more ABSTRACT Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many challenges. In this work, we present new techniques for realizing highly adaptive and reliable clock distribution for 3D ICs. Firstly, an efficient clock distribution topology without need of balanced H-tree is proposed. Secondly, a robust tunable-delay-buffer (TDB) circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry. Moreover, a design optimization flow is constructed for improving the adaptive clock design based on the thermal profiles. Experiment results show that the clock skews are significantly reduced using the proposed techniques.
This paper presents some results from phase-1 research into developing a beam steerer based on mi... more This paper presents some results from phase-1 research into developing a beam steerer based on micro-mechanical diffractive elements. The position of these elements is electrostatically controlled, to allow dynamic programming of a 2D phase function. Feasibility prototypes were constructed in the MUMPs polysilicon surface micromachine process.
A new proposal of applying surrogate-modeling in input-output buffer information specification (I... more A new proposal of applying surrogate-modeling in input-output buffer information specification (IBIS) is presented. It saves the IBIS data storage resource, extends the model utility to various process-voltage-temperature (PVT) simulations and eliminates the data interpolation deviations.
In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses an... more In this paper, we introduce a simple procedure to predict wiring delay in bi-directional buses and a way of properly sizing the driver for each of its port. In addition, we pr opose a simple calibration procedure to improve its delay prediction over the Elmore delay of the RC tree. The technique is fast, accurate, and ideal for implementation,in
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Papers by Paul Franzon