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A unique 64-row flat panel (FP) detector has been developed for sub-second multidetector-row CT (MDCT). The intent was to explore the image quality achievable with relatively inexpensive amorphous silicon (a-Si) compared to existing diagnostic scanners with discrete crystalline diode detectors. The FP MDCT system is a bench-top design that consists of three FP modules. Each module uses a 30 cm x 3.3 cm a-Si array with 576 x 64 photodiodes. The photodiodes are 0.52 mm x 0.52 mm, which allows for about twice the spatial resolution of most commercial MDCT scanners. The modules are arranged in an overlapping geometry, which is sufficient to provide a full-fan 48 cm diameter scan. Scans were obtained with various detachable scintillators, e.g. ceramic Gd IIO IIS, particle-in-binder Gd IIO IIS:Tb and columnar CsI:Tl. Scan quality was evaluated with a Catphan-500 performance phantom and anthropomorphic phantoms. The FP MDCT scans demonstrate nearly equivalent performance scans to a commercial 16-slice MDCT scanner at comparable 10 - 20 mGy/100mAs doses. Thus far, a high contrast resolution of 15 lp/cm and a low contrast resolution of 5 mm @ 0.3 % have been achieved on 1 second scans. Sub-second scans have been achieved with partial rotations. Since the future direction of MDCT appears to be in acquiring single organ coverage per scan, future efforts are planned for increasing the number of detector rows beyond the current 64- rows.

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 2 2 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly multiplier, digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-2 2 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 2 2 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas. Key words— Pipelined digit-slicing multiplier-less; Fast Fourier Transform (FFT); Verilog HDL; Xilinx; Radix 22 DIF SDF FFT.