Network on Chips

The design of scalable and reliable interconnection net-works for System on Chips (SoCs) introduce new design constraints not present in current multicomputer systems. Although regular topologies are preferred for building NoCs, heterogeneous blocks, fabrication faults and reliabil-ity ...

Network routers rely on an important hardware component, namely the switch fabric, responsible for forwarding incoming packets to their respective output ports according to a scheduling algorithm. A switch fabric mainly consists of buffering memories for temporary queuing and the scheduling unit(s) for forwarding.

In this paper, we revisit our previously proposed Network-on-Chip (NOC) based switch fabric architecture and: 1) propose an FPGA based hardware implementation of the NOC switch; 2) carry out performance tests, both via RTL simulations and actual execution on FPGA, under uniform traffic flows; and  3) present results in terms of throughput, average latency, and average bitrate. Our results show that our architecture i) performs as good as other buffering schemes/scheduling algorithms that theoretically achieve 100% throughput, ii) is at least as scalable as other architectures in terms of hardware cost, iii) is perfectly implementable and iv) introduces NOC concepts, which have originally been borrowed from computer networks, back into computer networks.

—The use of networks on chips has made it possible for computers to perform efficiently and at a high speed. This is because integrated circuits achieve a more elaborate connection between different systems' components. This paper examines the influence of the topology of an interconnection network in parallel computers. Both regular and irregular topologies are explored in an attempt to discover the advantages and disadvantages of each type. In addition, several regular and irregular topologies are investigated. The findings of this study assert that irregular topologies are more efficient than irregular topologies when it comes to performance. The results further suggest that irregular topologies are generally more efficient in some aspects such as chip area and energy consumption. On the other hand, regular topologies represent a more tempting solution when reusability and simplicity are primary concerns. Moreover, this study offers new insights into the functioning of both regular and irregular topologies in networks on chips.

Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.

Many different families of plastics are used in industry. The demand for the machining of plastics has recently increased. In most cases, traditional metal machining techniques and tools are being used in the machining of plastics. The present paper reviews the conventional mechanical machining of plastics. The cutting phenomena as indicated by the types of chips formed under various cutting conditions, and the cutting forces for the single-edge cutting of two broad types of plastics are discussed. When drilling plastics, the type of chip produced, the torque, and the thrust are considered. A general idea about the milling of plastics is shown. The possibility of grinding thermosets and thermoplastics using an open grinding wheel is discussed with reference to bond type, grit type, grit size and porosity. © 1995.

http://ac.els-cdn.com/0924013695019170/1-s2.0-0924013695019170-main.pdf?_tid=606a5b84-1d34-11e4-8f16-00000aab0f02&acdnat=1407307332_4796687b1dc145cacb860419bb2e0266

Network-on-Chip (NoC) is known as a scalable and high performance interconnect in Systems-on-Chip (SoCs) with multiple processing elements (PEs). Recently, the design paradigm of SoCs has shifted from static to dynamic run-time reconfigurable system. In these systems, the PEs can be loaded/unloaded on demand. Therefore, the NoC should be able to adapt as quickly as possible to the changes to maintain the performance of the systems. In this work, we present a non-intrusive runtime reconfigurable time-division-multiplexed circuit-switched NoC, XNoC, which offers the following benefits (1) it switches between different routes within a predictable latency that is strictly determined by the length of the route and the number of time slots; (2) the configuration process can be masked effectively by overlapping with communication and (3) the multi-cast service is supported with aggregate feedback from sink nodes. We propose an XSwitch which requires 3.5X less resource than the conventional switch with similar features. The overall resource cost of XNoC is also smaller than the most known NoC and the clock timing is up to 50% better. We also propose a novel distributed control plane to accelerate the reconfiguration process and to improve the scalability of NoC. The achieved reconfiguration speedup compared to the centralized control unit is up to 7.6X in certain conditions. On average, it takes only 74 clock cycles to activate a 12-hop connection.

Any consumer who opens a bag of potato or corn chips (or crisps in the UK) knows there is no time to waste to enjoy or share them. The convenience life span of chips is limited: it is the shelf or storage life and a very limited time once outside the bag. Many technologies converge to generate the desired effect as a black box, not only of the packaging but also of the chips themselves. The concept of paratext can be applied to printed messages on the package, including the brand name and other texts like advertising (epitexts), which can be expanded into the concept of parafood. These concepts help to discuss technological developments and interpret why this has recently become a negotiation zone for co-creation (see the Do us a flavor campaigns). They are symptoms of changing relations between production, research and development, marketing, and consumption. This paper pays special attention to back stories, underdog brand biographies and narratives about origin. The concept of brandwidth is introduced to sensitize about the limits of combining different stories about chips. A recent brand biography, a family history and a cookery book are used to discuss the phenomenon of cooking with Fritos. Together with the concepts of parafood, brandwidth and black boxes, more reflection and dialogue about the role of history and heritage in marketing put new challenging perspectives on the agenda.

Sistemas intra-chip (SoCs – Systems-on-Chip) são o atual paradigma utilizado na implementação de sistemas embarcados. O poder computacional destas plataformas possibilita a execução simultânea de diversas aplicações com diferentes requisitos. Neste cenário, o emprego de redes intra-chip (NoCs – Networks-on-chip) como infraestrutura de comunicação é uma realidade em pesquisas acadêmicas e projetos industriais. NoCs normalmente são vistas como alternativas à comunicação via barramento, oferecendo como principais vantagens a escalabilidade e suporte a comunicações paralelas.
Muitos trabalhos têm sido conduzidos na última década na área de NoCs, tratando da capacidade e potencial que esta infraestrutura de comunicação pode garantir aos SoCs. Devido à recente introdução do paradigma de circuitos integrados 3D e 2.5D, diversas pesquisas apontam a topologia tridimensional das NoCs como uma grande solução para SoCs que necessitam de centenas de núcleos de processamento. Motivados pela escassez de NoCs de código aberto que possuem nativamente a topologia de malha tridimensional e que sejam de fácil acesso a estudantes e desenvolvedores, o projeto da NoC Arke busca oferecer uma NoC estável, que dá suporte às topologias malha bidimensional e malha tridimensional, com diversos aspectos parametrizáveis, de fácil entendimento e independente de frameworks para geração automatizada de diferentes instâncias.
A NoC Hermes foi o principal objeto de estudos em relação ao funcionamento de uma NoC e ponto de partida para a implementação da NoC Arke. Ambas NoCs possuem muitas características em comum. Durante a criação da Arke buscou-se superar o modelo no qual ela havia sido moldada. Aspectos relacionados a facilidade de utilização, legibilidade do código, independência de framework, área ocupada pelo circuito, potência dissipada e tempo de roteamento foram pontos onde a Arke mostrou-se mais eficiente.

This paper describes designing efficient mesh topology Network-on-Chip system by employing MPLS protocol as an on-chip communication technique. Discrete-event simulator is developed in C++ to show the applicability of MPLS in providing efficient on-chip communication for multicore processing system-on-chip designs. Experimental results are compared with two simulators: wormhole equipped with virtual channels; and MPLS-based fat tree network-on-chip systems. Outstandingly, MPLS as on-chip communication means recorded better results than the wormhole +virtual channels in terms of throughput and packet end-to-end delay (latency).

Currently the industry moves to smaller process nodes even if the cost for yielding large dies continues to increase, moving to the 5nm and even 3nm nodes. Hence a chiplet-based design has been initiated and quickly gain attention from industry, academia and government agencies. This cutting edge approach became advantageous to break down a large die into smaller chiplets in order to improve yield and binning. In order to exploit this new approach the interconnect fabric connecting the nodes of the entire system should be of high importance to enable the properly distribution of the data. Each individual chiplet may contain its own local Network on Chip (NoC), which operates for intra-chiplet traffic. However the communication over chiplet-based systems is complicated enough, due to various routing algorithms and NoC topologies and an alternative solution is needed. In this paper we introduce an SDNoC(Software Define Network on Chip)-based communication protocol for chiplet-based systems, called MicroLET, which consists of a flexible and modular SDNoC architecture and 3 main phases: Handshake, Network Monitoring, Routing. An implementation of the SDNoC architecture and an evaluation of the proposed routing algorithm compared to the XY and the Odd-Even algorithms within different traffic scenarios is presented. Through the evaluation of the MicroLET protocol, it is proven that it could be a good candidate for the future chiplet-based systems.

The huge datacenters in the world - used in the social networks, researching and computing centers, and storage devices - have faced fundamental problem reflected in the need for high throughput to switch between the large numbers of virtual machines installed in these datacenters. The increased use of cloud applications will increase the need for greater numbers of virtual machines. In order to meet the requirements of this increase, it must be increased the hardware capabilities in the datacenters, through increasing the number of cores in the servers. Therefore, there is a need to provide network architecture that can connect all of these cores and chips very quickly. Consequently, it is necessary to enhance the virtual switching system to achieve the maximum integration and efficiency between the network segments, and analysis the scheduling and virtual queuing algorithms depending on the decisions from the experiences implemented using high-level source code and hardware description scheme with Xilinx platform.

Communication on- and off-chip now dominates the power and performance of modern electronic circuits. We propose the use of modern field programmable gate arrays (FPGAs) to investigate the communication properties of systems capable of simulating one billion neurons. Each FPGA provides gigabits of chip-to-chip communication bandwidth and on- and off-chip memory bandwidth. The FPGA structure allows us to control the allocation of this bandwidth in great detail allowing optimisations and analysis to be performed. We present our architectural explorations and initial findings.

Bluehive is a custom 64-FPGA machine targeted at scientific simulations with demanding communication re- quirements. Bluehive is designed to be extensible with a recon- figurable communication topology suited to algorithms with demanding high-bandwidth and low-latency communication, something which is unattainable with commodity GPGPUs and CPUs. We demonstrate that a spiking neuron algorithm can be efficiently mapped to Bluehive using Bluespec SystemVerilog by taking a communication-centric approach. This contrasts with many FPGA-based neural systems which are very focused on parallel computation, resulting in inefficient use of FPGA resources. Our design allows 64k neurons with 64M synapses per FPGA and is scalable to a large number of FPGAs.

—In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur. A protection mechanism is therefore required to prevent injection of malicious instructions or data across the system. We propose a self-contained Network-on-Chip (NoC) firewall at the network interface (NI) layer which, by checking the physical address against a set of rules, rejects untrusted CPU requests to the on-chip memory, thus protecting all legitimate processes running in a multicore SoC. To sustain high performance, we implement the firewall in hardware, with rule-checking performed at segment-level based on deny rules. Furthermore, to evaluate its impact, we develop a novel framework on top of gem5 simulation environment , coupling ARM technology and an instance of a commercial point-to-point interconnect from STMicroelectronics (STNoC). Simulation tests include scenarios in which legitimate and malicious processes, running in different CPUs, request access to shared memory. Our results indicate that a firewall implementation at the NI can have a positive effect on network performance by reducing both end-to-end network delay and power consumption. We also show that our coarse-grain firewall can prevent saturation of the on-chip network and performs better than fine-grain alternatives that perform rule checking at page-level. Simulation results are accompanied with field measurements performed on a Zedboard platform running Linux, whereas the NoC Firewall is implemented as a reconfigurable, memory-mapped device on top of AMBA AXI4 interconnect fabric.

Silicon interposer technology (“2.5D” stacking)
enables the integration of multiple memory stacks with a
processor chip, thereby greatly increasing in-package memory
capacity while largely avoiding the thermal challenges of 3D
stacking DRAM on the processor. Systems employing interposers
for memory integration use the interposer to provide
point-to-point interconnects between chips. However, these
interconnects only utilize a fraction of the interposer’s overall
routing capacity, and in this work we explore how to take
advantage of this otherwise unused resource.
We describe a general approach for extending the architecture
of a network-on-chip (NoC) to better exploit the additional
routing resources of the silicon interposer. We propose an
asymmetric organization that distributes the NoC across both
a multi-core chip and the interposer, where each sub-network
is different from the other in terms of the traffic types, topologies,
the use or non-use of concentration, direct vs. indirect
network organizations, and other network attributes. Through
experimental evaluation, we show that exploiting the otherwise
unutilized routing resources of the interposer can lead to
significantly better performance.

Hierarchical  topologies  are  frequently  proposed  for  large  NetworksonChip  (NoCs). Hierarchical architectures utilize, at the upper levels, long links of the order of the die size. RC  delays of long links might reach dozens of clock cycles in advanced technology nodes, if delay reduction techniques (e.g. wire sizing and repeater insertion) are not applied. Some proposals assume  that  long  links  can  be  adjusted  to  satisfy  timing  requirements,  but  lack  a  deep evaluation  of  the  tradeoffs  and  costs.  Other  proposals  assume  that  long links  must  be pipelined, but do not provide a comprehensive justification.
In this paper we evaluate the efficiency and the system costs of wire sizing and repeater insertion  as  methods  to  reduce  link  delays  in  hierarchical  NoCs.  We  present  a  unified  interconnect cost function that accounts for power and wiring overheads of these methods. Then, we quantify the costs of modifying long links in typical hierarchical NoCs for different
target clock frequencies and technology nodes. Although long links might undergo aggressive adjustments, we find these overall costs to be low at the system level for typical cases, taking into  account  that  there  are  only  a  few  long  links  in  most  proposed  hierarchical  NoC architectures.

Network-on-Chip (NoC) is a paradigm proposed to satisfy the communication demands of future Systems-on-Chip (SoC). The main components of an NoC are the network adapters, routing nodes, and network interconnect links. Reducing area and power consumption has higher priority in the case of on-chip networks compared to conventional off-chip networks. This paper presents an area efficient design for the routing node component of an NoC. T he area efficiency is obtained by applying the concept of a pipelined design as well as the use of custom IP (intellectual property) cores.

The advent of System-on-Chip (SoCs), has brought about a need to increase the scale of multi-core chip networks. Bus Based communications have proved to be limited in terms of performance and ease of scalability, the solution to both bus-based and Point-to-Point (P2P) communication systems is to use a communication infrastructure called Network-on-Chip (NoC). Performance of NoC depends on various factors such as network topology, routing strategy and switching technique and traffic patterns. In this paper, we have taken the initiative to compile together a comparative analysis of different Network on Chip infrastructures based on the classification of routing algorithm, switching technique, and traffic patterns. The goal is to show how varied combinations of the three factors perform differently based on the size of the mesh network, using NOXIM, an open source SystemC Simulator of mesh-based NoC. The analysis has shown tenable evidence highlighting the novelty of XY routing algorithm.

As the number of modules grows, performance scalability of planar topology Networks-on-Chip (NoCs) becomes limited due to increasing hop-distances, since long paths involve more routers. The growing hop-distance affects both end-to-end network latency and overall network saturation. Hierarchical topologies provide routes with shorter hop-distances and therefore are more adequate for large systems. The introduction of hierarchical NoCs poses new challenges as they should provide the shortest hop-distance for as many as possible source–destination pairs with minimal interference among packets, at the lowest hardware and system costs.

In this paper, a framework for design and dynamic management of hierarchical NoCs is introduced. The design space of hierarchical NoCs is explored under cost and performance constraints. A dynamic management scheme termed DTrD (Dynamic Traffic Distribution) is proposed. DTrD enables to dynamically adapt the routing policy in hierarchical NoCs to varying traffic conditions. Finally, a set of guidelines is formulated for proper design and dynamic control of hierarchical NoCs.

Abstract: Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power System-on-chip designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores that are not used in an application can be shutdown, while the other islands can still be operational. When one or more of the islands are shutdown, the interconnect should allow the communication between islands that are operational. For this, the NoCs has to be designed efficiently to allow shutdown of VIs, thereby reducing the leakage power consumption. Here in this paper, the methods to design NoC topologies that provide such a support for both 2D and 3D ICs presented. The concept of VIs need to be considered during topology synthesis phase itself is also presented. This paper shows the benefits of migrating to 3D-stacked chips for realistic applications that have multiple VIs.

This paper describes designing an efficient mesh topology Network-on-Chip system by employing MPLS protocol as an on-chip communication technique. A discrete-event simulator is developed in C++ to show the applicability of MPLS in providing efficient on-chip communication for multicore processing system-on-chip designs. Experimental results are compared with two simulators: wormhole equipped with virtual channels; and MPLS-based fat tree network-on-chip systems. Outstandingly, MPLS as on-chip communication means recorded better results than the wormhole +virtual channels in terms of throughput and packet end-to-end delay (latency).

A network on a chip is a network based communication subsystem on an integrated circuit, most typically between modules in a system on chip (SoC). The modules on the IC are typically semiconductor IP cores schematizing various functions of the computer system and are designed to be modular in the sense of network science. The network on chip is a switching network between SOC in the router. Deadlock and Livelock freedom in Routing is one of current issue in NoC routing. The Deadlock and livelock freedom prohibiting certain routing turns. NOC based architecture uses great amount of power. To schedule the processes, a round-robin scheduler generally allocate time for sharing, giving each job based on time slot (its allowance of CPU time) and interrupts the duty if it's not completed by them. When the duty is resumed next time a time slot is assigned to it. If the process ends or changes its state to waiting during its fixed time quantum, the scheduler selects the primary process within the ready queue to execute. In the absence of time sharing, or if the quantum were large relative to the size of the role, a process that produced large jobs would be preferred over other processes. Round-robin algorithm is a pre algorithm technique as the scheduler forces the process out of the CPU once the time allocation expires. Round robin algorithm reduces the dynamic power in the module. The algorithm is written by using Verilog HDL and tested on Xilinx 14.7 ISE and the algorithm is implemented by using FPGA VERTEX5 kit.

The design of more complex systems becomes an increasingly difficult task because of different issues related to latency, design reuse, throughput and cost that has to be considered while designing. In Real-time applications there are different communication needs among the cores. When NoCs (Networks on chip) are the means to interconnect the cores, use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution. But unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs in extra dissipation for the mean case, which is much more frequent. Reconfigurable router architecture for NOC is designed for processing elements communicate over a second communication level using direct-links between another node elements. Several possibilities to use the router as additional resources to enhance complexity of modules are presented. The reconfigurable router is evaluated in terms of area, speed and latencies. The proposed router was described in VHDL and used the ModelSim tool to simulate the code. Analyses the average power consumption, area, and frequency results to a standard cell library using the Design Compiler tool. With the reconfigurable router it was possible to reduce the congestion in the network, while at the same time reducing power dissipation and improving energy.

Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional bus-based architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.

As the number of applications and programmable units in CMPs and MPSoCs increases, the Network-on-Chip (NoC) encounters diverse and time dependent traffic loads. This trend motivates the introduction of NoC load-balanced, adaptive routing mechanisms that achieve higher throughput as compared with traditional oblivious routing schemes that are perceived better suited for hardware implementations. However, an efficient adaptive routing scheme should base its decisions on the global state of the system rather than on local or regional congestion signals as is common in current adaptive routing schemes. In this paper we introduce a novel paradigm of NoC centralized adaptive routing, and a specific design for mesh topology. Our scheme continuously monitors the global traffic load in the network and modifies the routing of packets to improve load balancing accordingly. In our specific mesh-based design, XY or YX routes are adaptively selected for each source-destination pair. We show that while our implementation is scalable and lightweight in hardware costs, it outperforms distributed adaptive routing schemes in terms of load balancing and throughput.

The Network on Chip (NoC) has developed as a substitute for wired or interconnection network for System on Chip (SoC). It acts as a way to reduce existing problems of interference, bandwidth desideratum, and potential and makes clock distribution work easier. The performance of the network can be evaluated by numerous factors but latency and throughput are primary characteristics of measurement. So, this paper contains study and evaluation of various existing topologies and their operational evaluation is done on the basis of latency and throughput.

To enable data transmission speeds that surpass the 5th Generation (5G) standards for telecommunications, scientists from Nanyang Technological University, Singapore (NTU Singapore) and Osaka University in Japan have built a new chip using a concept called photonic topological insulators. [31] Laser light traveling through ornately microfabricated glass has been shown to interact with itself to form self-sustaining wave patterns called solitons. [30] Scientists have developed a new type of laser that can deliver high amounts of energy in very short bursts of time, with potential applications in eye and heart surgery or the engineering of delicate materials. [29] So far, the researchers' calculations do not extend to the behavior of a zero-charge polyacetylene soliton that carries spin, but they expect that it should be possible to manipulate this with a magnetic field gradient. [28] Researchers have developed the first materials that can permanently change from solid to liquid, or vice versa, when exposed to light at room temperature, and remain in the new phase even after the light is removed. [27] A solid can serve as a medium for heat and sound wave interactions just like a fluid does for thermoacoustic engines and refrigerators-resulting in leak-free machines that can stay operating longer. [26] Like watchmakers choosing superior materials to build a fine timepiece, physicists at the Centre for Quantum Technologies (CQT) at the National University of Singapore have singled out an atom that could allow them to build better atomic clocks. [25] Yale physicists have uncovered hints of a time crystal-a form of matter that "ticks" when exposed to an electromagnetic pulse-in the last place they expected: a crystal you might find in a child's toy. [24] The research shows that concentrated electrolytes in solution affect hydrogen bonding, ion interactions, and coordination geometries in currently unpredictable ways. [23] An exotic state of matter that is dazzling scientists with its electrical properties, can also exhibit unusual optical properties, as shown in a theoretical study by researchers at A*STAR. [22]

Despite that there is a " one-to-many " mapping between scheduling algorithms and scheduler implementations, only a few studies have discussed the challenges and consequences of translating between these two system models. There has been an argument that a wide gap exists between scheduling theory and scheduling implementation in practical systems, where such a gap must be bridged to obtain an effective validation of embedded systems. In this paper, we introduce a technique called " Scheduler Test Case " (STC) aimed at bridging the gap between scheduling algorithms and scheduler implementations in single-processor embedded systems implemented using Time-Triggered Cooperative (TTC) architectures. We will demonstrate how the STC technique can provide a simple and systematic way for documenting, verifying (testing) and comparing various TTC scheduler implementations on particular hardware. However, STC is a generic technique that provides a black-box tool for assessing and predicting the behaviour of representative implementation sets of any real-time scheduling algorithm.

Traffic simulation software is becoming increasingly popular as more cities worldwide use it to better
manage their crowded traffic networks. An important requirement for such software is the ability to
produce accurate results in real time, requiring great computation resources. This work proposes an ASICbased
hardware accelerated approach for the AIMSUN traffic simulator, taking advantage of repetitive
tasks in the algorithm. Different system configurations using this accelerator are also discussed. Compared
with the traditional software simulator, it has been found to improve the performance by as much as 9x
when using a single processing element approach, or more depending on the chosen hardware
configuration.

The shortcomings of conventional bus architectures are in terms of scalability and the ever increasing demand of more bandwidth. And also the feature size of sub-micron domain is decreasing making it difficult for bus architectures to fulfill the requirements of modern System on Chip (SoC) systems. Network on chip (NoC) architectures presents a solution to the earlier mentioned shortcomings by employing a packet based network for inter IP communications. A pivotal feature of NoC systems is the topology in which the system is arranged. Several parameters which are topology dependent like hop count, path diversity, degree and other various parameters affect the system performance. We propose a novel topology forNoC architecture which has been thoroughly compared with the existing topologies on the basis of different network parameters.

—In the future almost every consumer electronics device will be connected to an ecosystem of third-party partners providing services such as payment, streaming content, and so on. Present work aims to expose the foundations of a secure environment by ensuring security on the edge devices. MPSoCs are widely used in edge devices due to their capability to execute multiple applications in single-chips. To achieve the targeted security level against physical adversaries, all communications between the MPSoC and its environment must be protected. In an MPSoC multiple processing elements such as CPUs send requests to different on-chip memories. Network-on-chip has been proposed for MPSoC design, aiming at increasing performance and reducing power compared to on-chip buses. Tailoring the NoC to application(s) takes place usually at design-time. The selection of NoC parameter values affects both performance and power, while configuring them unwisely can result in unnecessary area overhead and chip cost. In the present work we concentrate on a commercial interconnect called STNoC from STMicroelectronics. We keep the NoC parameters fixed, and we explore the effects from the variation of other parameters, such as the injection rate of the packets transmitted by the CPUs, and the activation/deactivation of a security mechanism integrated in the network interface of the NoC, for multiple traffic scenarios with each one representing different amount of legal and malicious requests, for different mappings, and for different node setups. Experimental results, reveal the conditions under which the NoC starts experiencing saturation phenomena.

In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocation schemes which affect the performance of the system. In this paper we test the pre-existing proposed algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic
and cluster approaches are proposed along with the  optimization using bio-inspired algorithm. The proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark and has been compared with the existing mapping algorithm spiral and crinkle and has shown better
reduction in the communication energy consumption and shows improvement in the performance of the system. On performing experimental analysis of proposed algorithm results shows that average reduction in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%. Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.

This is a high performance NoC Router that handles precise localizations of the faulty parts of the NoC. The
proposed router is based on new error detection mechanisms suitable for dynamic NoCs, where the position of
processor elements or faulty blocks varies during runtime. Indeed, I propose an online Error detection
mechanism using CRC Algorithm. Proposed mechanism is able to discriminate permanent and transient errors
and localize precisely the position of the faulty blocks in the NoC routers, while preserving the throughput, the
network load, and the data packet latency.