Network on chip

The design of scalable and reliable interconnection net-works for System on Chips (SoCs) introduce new design constraints not present in current multicomputer systems. Although regular topologies are preferred for building NoCs, heterogeneous blocks, fabrication faults and reliabil-ity ...

This paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called 'N-byte RCC (Repetition of Computation and Combination)''. This algorithm is the iterative process of message computation by the 'slicing-by-4' and combination through the 'zero block lookup tables'. This algorithm can parallelize the CRC calculation with any number of processors. In order to verify the performance of our algorithm, we employ two different communication architectures; the single bus architecture and the 1-star topology NoC (Network on Chip) architecture. With respect to those architectures, we explore our parallel algorithm by using TLM (Transaction Level Model). From the simulation results, we present that the proposed parallel CRC algorithm with BUS and NoC architectures reduces the processing time by 28 percent and 38 percent, respectively, compared to the 'slicing-by-8' which is the fastest algorithms among other software based algorithms. Furthermore, the 1-star NoC architecture of the parallel CRC shows higher performance than the single bus architecture regardless of the number of processors.

In this paper, we address the problem of high-level ex- ploration of Network-on-Chip (NoC) architectures to early evaluate power/performance trade-offs. The main goal of this work is to pro- pose a methodology supported by a design framework (namely, PI- RATE ) to generate and to simulate a configurable NoC-IP core for the power/performance exploration of the on-chip interconnection network. The NoC-IP core is composed of a set of parameterized modules, such as interconnection elements and switches, to form different on-chip micro- network topologies. The proposed framework has been applied to explore several network topologies by varying the workload and to analyze a case study designed for cryptographic hardware acceleration in high perfor- mance web server systems.

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second power supply. A 0.18mum CMOS testchip shows 10.5times energy savings at a 50mV swing compared to full-swing repeated wires, and a 3times gain in wire bandwidth

... EMBEDDED SYSTEMS Mehdi Modarressi Computer Engineering Dept. Sharif University of Technology, Tehran, Iran modarressi@ce.sharif.edu Shaahin Hessabi Computer Engineering Dept. Sharif University of Technology, Tehran, Iran hessabi@sharif.edu ...

Bio-inspired paradigms such as spiking neural networks (SNNs) offer the potential to emulate the repairing and adaptive ability of the brain. This paper presents EMBRACE-FPGA, a scalable, configurable network on chip (NoC)-based SNN architecture, implemented on Xilinx Virtex II-Pro FPGA hardware. In association with a genetic algorithm-based hardware evolution platform, EMBRACE-FPGA provides a computing platform for intrinsic hardware evolution, which can be used to explore the evolution and adaptive capabilities of hardware SNNs. Results demonstrate the application of the hardware SNN evolution platform to solve the XOR benchmark problem.

The voltage/frequency island (VFI) design paradigm is a practical architecture for energy-efficient networks-on-chip (NoC) systems. In VFI-based NoC systems, each island can be operated with different voltage and clock frequency and thus it is important to carefully partition processing elements (PEs) into islands based on their workloads and communications. In this paper, we propose an energy-efficient design scheme that optimizes energy consumption and hardware costs in VFI-based NoC systems. Since on-chip networks take up a substantial portion of system power budget in NoC-based systems, the proposed scheme uses communication-aware VFI partitioning and tile mapping/routing algorithms to minimize the inter-VFI communications. Experimental results show that the proposed design technique can reduce communication energy consumption by 32–51% over existing techniques and total energy consumption by 3–14%.

Micro/nanostructure photonic devices offer a variety of enabling properties, including low power-consumption, cost-efficient, compact size, and reliability. These distinctive features have been exploited in a wealth of applications ranging from telecommunication and optical interconnect to photonic network on chip. In this paper, we review two main classes of micro/nanostructure photonic devices, to provide the kinds of functions for optical signal processing.