Research Interests:
Research Interests:
Abstract This work presents an implementation of a direct torque control (DTC) strategy, which is used to control induction motors. Following a tendency in this research area, the algorithm proposed is implemented in a unique FPGA... more
Abstract This work presents an implementation of a direct torque control (DTC) strategy, which is used to control induction motors. Following a tendency in this research area, the algorithm proposed is implemented in a unique FPGA substrate, which allows for a faster ...
Research Interests:
ABSTRACT Direct Torque Control of induction motors is the latest step in motor drives. Hysteresis band amplitude choice is one of the initial difficulties involved in the technique since it determines ripple frequencies and amplitude... more
ABSTRACT Direct Torque Control of induction motors is the latest step in motor drives. Hysteresis band amplitude choice is one of the initial difficulties involved in the technique since it determines ripple frequencies and amplitude error of control variables. Correlation between hysteresis bands, ripple frequencies and error amplitudes is due to the establishment of limit cycles in inner control loops. In this paper, an alternative structure which simplifies designers work through the control of flux and torque error amplitudes by means of dithering is presented. A simulation environment developed in MATLAB/ Simulink is used to obtain the results. This environment takes into account the dynamic behavior of each individual block allowing for the project and test of controlling structures for DTC in an inexpensive way.
Research Interests:
Research Interests: Computer Science, Computer Architecture, Distributed Computing, Computational Modeling, Energy Consumption, and 14 moreSoc, Computation, Computer Model, Asynchronous Communication, System on Chip, Networks on Chip (NoC), Communication Channels, Coverage, System on a Chip, Network on chip, Interconnection, Wireless Sensor Network, Network on a Chip, and Hardware architecture
Abstract This paper presents the implementation and evaluation of a hardware and software co-simulation tool. Different simulators, which can be geographically distributed, compose this environment. The communication between simulators is... more
Abstract This paper presents the implementation and evaluation of a hardware and software co-simulation tool. Different simulators, which can be geographically distributed, compose this environment. The communication between simulators is done using a co-simulation backplane. The co-simulation backplane reads a file describing how the modules are connected, automatically launches the simulators and controls the simulation process. A case study is used as a benchmark to validate the implementation and to evaluate the ...
Research Interests:
Research Interests: Management, Computer Science, Algorithms, Computer Architecture, Design, and 15 moreFPGA, HTML, Field Programmable Gate Array, Circuits, Pipelines, Partial Reconfiguration, Control Reconfiguration, Network Flow, Integrated Circuit, Multimedia Application, Coarse Grained Soil, Embedded System, Dynamic Reconfiguration, Floorplanning, and Hierarchical
Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory to cope with transient and permanent faults. This issue is even more relevant in nanotechnologies due to process variability, aging effects,... more
Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory to cope with transient and permanent faults. This issue is even more relevant in nanotechnologies due to process variability, aging effects, and susceptibility to upsets, among other factors. The literature presents isolated solutions to deal with faults in the MPSoC communication infrastructure. In this context, one gap to be fulfilled is to integrate all layers, resulting in a solution to cope with NoC faults from the physical layer up to the application layer. The goal of this work is to present a runtime integrated approach to cope with NoC faults in MPSoCs. The original contribution is the proposal of a set of hardware and software mechanisms to ensure both efficient and reliable communication in NoC-based MPSoCs. The proposal has an acceptable silicon area overhead and a small memory footprint. Experiments demonstrate that benchmarks (synthetic and real MPSoC applications) were simulated with thousands of random fault injections, and all of them were executed correctly. Moreover, the average application execution time overhead is lower than 0.5%. This suggests the proposed fault tolerant method could be used in applications with reliability and performance constraints.
Research Interests:
Research Interests:
Research Interests:
Research Interests:
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy consumption. Traffic is seen as an important factor... more
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy consumption. Traffic is seen as an important factor affecting the problem of mapping applications into NoCs having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (SoC). Experiments showed that failing to consider the bit transitions influence on traffic inevitably leads to an energy estimation error. This error is proportional to the amount of bit transitions in transmitted packets. In applications that present a large number of packets exchange, the error is propagated, significantly affecting the mapping results. This paper proposes a high-level application model that captures the traffic effect and uses it to describe the behavior of applications. In order to evaluate the quality of the proposed model, a set of embedded systems were described using both, a previously proposed model (that does not capture the traffic effect), and the model proposed here. Comparing the resulting mappings, those derived from the proposed model showed improvements in energy savings with regard to the other model for all experiments.
Research Interests:
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconfigurable processors suffer from the lack of a... more
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconfigurable processors suffer from the lack of a pre-established instruction set, making them difficult to program. As intermediate choice, reconfigurable coprocessors systems (RCSs) contain dedicated hardware (coprocessors) coupled to a standard processor core to accelerate specific tasks, allowing inserting or substituting hardware functionalities at ...
Research Interests:
Research Interests:
Current technology allows building integrated circuits (ICs) complex enough to contain all major elements of a complete end product, which are accordingly called Systems-on-Chip (SoCs)[1]. A SoC usually contains one or more programmable... more
Current technology allows building integrated circuits (ICs) complex enough to contain all major elements of a complete end product, which are accordingly called Systems-on-Chip (SoCs)[1]. A SoC usually contains one or more programmable processors, on-chip memory, peripheral devices, and specifically designed complex hardware modules. SoCs are most often implemented as a collection of reusable components named intellectual property cores (IP cores or cores). An IP core is a complex hardware module, created for reuse and that ...
Research Interests:
Research Interests: Computer Science, Design, Theory, Performance, Traffic modelling, and 15 moreDesign process, QoS, Quality of Service, Measurement, Traffic Modeling, Network Performance, Traffic Flow, Experimentation, Dimensioning, Network on chip, Networks on Chip, Model Complexity, Resource Utilization, Network on a Chip, and Network traffic Simulation
Research Interests:
Research Interests: Engineering, Computer Science, Routing algorithm, Performance Evaluation, Computer Network, and 12 moreTraffic Modeling, Network Performance, Spatial Distribution, Hot Spot, System on a Chip, Network on chip, Mesh Networking, MESH NETWORK, Experimental Measurement, Network Traffic, Virtual Channel, and Network Interface
Abstract Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of... more
Abstract Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a scenario that requires the use of dynamic task mapping. Static mappings have as main advantage the global view of the system, while dynamic mappings normally ...
Research Interests:
The goal of this paper is to evaluate the performance of embedded digital systems generated from a system level description language. The target language is SDL, which is automatically synthesized with a codesign tool, resulting in VHDL... more
The goal of this paper is to evaluate the performance of embedded digital systems generated from a system level description language. The target language is SDL, which is automatically synthesized with a codesign tool, resulting in VHDL and C descriptions. The codesign tool is responsible for software, hardware and communication synthesis. Two case studies are presented, exploring area and delay
Research Interests:
Research Interests:
Research Interests: Engineering, Computer Science, Routing algorithm, Packet Switching, Computer Hardware, and 15 moreDistributed System, Computer Network, Case Study, Integration, Implementation, Circuit Design, Chip, Network on chip, Network Topology, Digital Circuit, Integrated Circuit, Integr, Bandwidth, Embedded System, and Prototype
Research Interests:
Abstract-This paper describes the design and prototyping of EMS, a telecommunication intellectual property soft-core developed in the scope of industry-academia cooperation. EMS performs insertion (mapping) and extraction (demapping) of... more
Abstract-This paper describes the design and prototyping of EMS, a telecommunication intellectual property soft-core developed in the scope of industry-academia cooperation. EMS performs insertion (mapping) and extraction (demapping) of EI channels into/from Synchronous Digital Hierarchy (SDH) frames. The basic SDH frame is transmitted in 155.52 Mbps rate, allowing to pack up to sixty-three 2.048 Mbps El channels. El channels belong to the Plesiochronous Digital Hierarchy (PDH). The paper addresses the solution of several ...
Research Interests:
This paper discusses several aspects of the modeling and description of computational systems. A metamodel for representing the process of obtaining an abstract description (ie a model) of a computational system is proposed and justified.... more
This paper discusses several aspects of the modeling and description of computational systems. A metamodel for representing the process of obtaining an abstract description (ie a model) of a computational system is proposed and justified. To concretely illustrate the compromises involved in modeling computational systems, the paper shows a case study of specifying a telecom hardware module and describing it in two languages with widely different modeling assumptions, namely VHDL and SDL. The comparison of the ...
Research Interests:
RESUMO Este trabalho apresenta a implementação de um ambiente de simulação conjunta entre módulos hardware e software. Este ambiente é composto por diversos simuladores para cada módulo do sistema, que podem estar distribuídos em uma WAN... more
RESUMO Este trabalho apresenta a implementação de um ambiente de simulação conjunta entre módulos hardware e software. Este ambiente é composto por diversos simuladores para cada módulo do sistema, que podem estar distribuídos em uma WAN (wide area network). Os simuladores se comunicam com uso de sockets através de um programa roteador que estabelece a conexão entre todos os módulos. Um simples estudo de caso é apresentado com o objetivo de validar esta metodologia de co-simulação. Palavras- ...
Research Interests:
Research Interests:
Abstract ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffers from fixed hardware after design, while ASIPs and reconfigurable processors suffer from the lack of a... more
Abstract ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffers from fixed hardware after design, while ASIPs and reconfigurable processors suffer from the lack of a pre-established instruction set, making it difficult to program. An intermediate solution, reconfigurable coprocessors systems (RCSs), contains dedicated hardware (coprocessors) coupled to a standard processor core to accelerate specific tasks, being possible to insert or substitute hardware functionalities ...
Research Interests:
Research Interests:
Abstract Dynamically Reconfigurable Systems (DRSs) have the potential to provide hardware with flexibility similar to that of software. At the same time, they may lead to better performance and smaller system size. However, there is a... more
Abstract Dynamically Reconfigurable Systems (DRSs) have the potential to provide hardware with flexibility similar to that of software. At the same time, they may lead to better performance and smaller system size. However, there is a clear lack of support devices, tools and design flows adequate for such systems. One of the main problems for enabling dynamically reconfigurable systems is the unavailability of efficient methods to control the hardware configuration process. The main contribution of this work is the proposal of a ...
Research Interests:
Research Interests:
Research Interests:
The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that... more
The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.
Research Interests:
Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory to cope with transient and permanent faults. This issue is even more relevant in nanotechnologies due to process variability, aging effects,... more
Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory to cope with transient and permanent faults. This issue is even more relevant in nanotechnologies due to process variability, aging effects, and susceptibility to upsets, among other factors. The literature presents isolated solutions to deal with faults in the MPSoC communication infrastructure. In this context, one gap to be fulfilled is to integrate all layers, resulting in a solution to cope with NoC faults from the physical layer up to the application layer. The goal of this work is to present a runtime integrated approach to cope with NoC faults in MPSoCs. The original contribution is the proposal of a set of hardware and software mechanisms to ensure both efficient and reliable communication in NoC-based MPSoCs. The proposal has an acceptable silicon area overhead and a small memory footprint. Experiments demonstrate that benchmarks (synthetic and real MPSoC applications) were simulated with thousands of random fault injections, and all of them were executed correctly. Moreover, the average application execution time overhead is lower than 0.5%. This suggests the proposed fault tolerant method could be used in applications with reliability and performance constraints.
Research Interests:
The design of reliable MPSoCs is mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative... more
The design of reliable MPSoCs is mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative fault-free paths to a given destination. This paper presents a novel fault-tolerant communication protocol that takes advantage of the NoC parallelism to provide alternative paths between any source-target pair of processors, even in the presence of multiple faults. At the application layer, the method is seen as a typical MPI-like message passing protocol. At the lower layers, the method consists of a software kernel layer that monitors the regularity of message exchanges between pairs of tasks. If a message is not delivered in a certain time, the software fires a path finding mechanism implemented in hardware, which guarantees complete network reachability. The proposed approach determines new paths quickly, and the costs of extra silicon area and memory usage are small.
Research Interests:
Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the... more
Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based approaches on test time is not clear, and (c) a computer aided test tool must be able to support different types of NoC designs. This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures. Moreover, this paper presents a new test scheduling algorithm for NoC TAMs which does not require any NoC timing detail and it can easily model NoCs of different topologies. The experimental results evaluate the proposed algorithm for NoC TAMs with an exiting algorithm for dedicated TAMs. The results demonstrate that, on average, 24% (up to 58%) of the total global wires can be eliminated if dedicated TAMs are not used. Considering the reduced amount of dedicated test resources with NoC TAM, the test time of NoC TAM is only, on average, 3.88% longer compared to dedicated TAMs.
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This... more
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing