16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.
Abstract This work presents an implementation of a direct torque control (DTC) strategy, which is... more Abstract This work presents an implementation of a direct torque control (DTC) strategy, which is used to control induction motors. Following a tendency in this research area, the algorithm proposed is implemented in a unique FPGA substrate, which allows for a faster ...
ABSTRACT Direct Torque Control of induction motors is the latest step in motor drives. Hysteresis... more ABSTRACT Direct Torque Control of induction motors is the latest step in motor drives. Hysteresis band amplitude choice is one of the initial difficulties involved in the technique since it determines ripple frequencies and amplitude error of control variables. Correlation between hysteresis bands, ripple frequencies and error amplitudes is due to the establishment of limit cycles in inner control loops. In this paper, an alternative structure which simplifies designers work through the control of flux and torque error amplitudes by means of dithering is presented. A simulation environment developed in MATLAB/ Simulink is used to obtain the results. This environment takes into account the dynamic behavior of each individual block allowing for the project and test of controlling structures for DTC in an inexpensive way.
Proceedings. 15th Symposium on Integrated Circuits and Systems Design
Abstract This paper presents the implementation and evaluation of a hardware and software co-simu... more Abstract This paper presents the implementation and evaluation of a hardware and software co-simulation tool. Different simulators, which can be geographically distributed, compose this environment. The communication between simulators is done using a co-simulation backplane. The co-simulation backplane reads a file describing how the modules are connected, automatically launches the simulators and controls the simulation process. A case study is used as a benchmark to validate the implementation and to evaluate the ...
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design - SBCCI '14, 2014
Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory ... more Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory to cope with transient and permanent faults. This issue is even more relevant in nanotechnologies due to process variability, aging effects, and susceptibility to upsets, among other factors. The literature presents isolated solutions to deal with faults in the MPSoC communication infrastructure. In this context, one gap to be fulfilled is to integrate all layers, resulting in a solution to cope with NoC faults from the physical layer up to the application layer. The goal of this work is to present a runtime integrated approach to cope with NoC faults in MPSoCs. The original contribution is the proposal of a set of hardware and software mechanisms to ensure both efficient and reliable communication in NoC-based MPSoCs. The proposal has an acceptable silicon area overhead and a small memory footprint. Experiments demonstrate that benchmarks (synthetic and real MPSoC applications) were simulated with thousands of random fault injections, and all of them were executed correctly. Moreover, the average application execution time overhead is lower than 0.5%. This suggests the proposed fault tolerant method could be used in applications with reliability and performance constraints.
Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05, 2005
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores th... more This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy consumption. Traffic is seen as an important factor affecting the problem of mapping applications into NoCs having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (SoC). Experiments showed that failing to consider the bit transitions influence on traffic inevitably leads to an energy estimation error. This error is proportional to the amount of bit transitions in transmitted packets. In applications that present a large number of packets exchange, the error is propagated, significantly affecting the mapping results. This paper proposes a high-level application model that captures the traffic effect and uses it to describe the behavior of applications. In order to evaluate the quality of the proposed model, a set of embedded systems were described using both, a previously proposed model (that does not capture the traffic effect), and the model proposed here. Comparing the resulting mappings, those derived from the proposed model showed improvements in energy savings with regard to the other model for all experiments.
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a giv... more ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconfigurable processors suffer from the lack of a pre-established instruction set, making them difficult to program. As intermediate choice, reconfigurable coprocessors systems (RCSs) contain dedicated hardware (coprocessors) coupled to a standard processor core to accelerate specific tasks, allowing inserting or substituting hardware functionalities at ...
New Algorithms, Architectures and Applications for Reconfigurable Computing
Current technology allows building integrated circuits (ICs) complex enough to contain all major ... more Current technology allows building integrated circuits (ICs) complex enough to contain all major elements of a complete end product, which are accordingly called Systems-on-Chip (SoCs)[1]. A SoC usually contains one or more programmable processors, on-chip memory, peripheral devices, and specifically designed complex hardware modules. SoCs are most often implemented as a collection of reusable components named intellectual property cores (IP cores or cores). An IP core is a complex hardware module, created for reuse and that ...
2009 International Symposium on System-on-Chip, 2009
Abstract Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perfo... more Abstract Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a scenario that requires the use of dynamic task mapping. Static mappings have as main advantage the global view of the system, while dynamic mappings normally ...
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.
Abstract This work presents an implementation of a direct torque control (DTC) strategy, which is... more Abstract This work presents an implementation of a direct torque control (DTC) strategy, which is used to control induction motors. Following a tendency in this research area, the algorithm proposed is implemented in a unique FPGA substrate, which allows for a faster ...
ABSTRACT Direct Torque Control of induction motors is the latest step in motor drives. Hysteresis... more ABSTRACT Direct Torque Control of induction motors is the latest step in motor drives. Hysteresis band amplitude choice is one of the initial difficulties involved in the technique since it determines ripple frequencies and amplitude error of control variables. Correlation between hysteresis bands, ripple frequencies and error amplitudes is due to the establishment of limit cycles in inner control loops. In this paper, an alternative structure which simplifies designers work through the control of flux and torque error amplitudes by means of dithering is presented. A simulation environment developed in MATLAB/ Simulink is used to obtain the results. This environment takes into account the dynamic behavior of each individual block allowing for the project and test of controlling structures for DTC in an inexpensive way.
Proceedings. 15th Symposium on Integrated Circuits and Systems Design
Abstract This paper presents the implementation and evaluation of a hardware and software co-simu... more Abstract This paper presents the implementation and evaluation of a hardware and software co-simulation tool. Different simulators, which can be geographically distributed, compose this environment. The communication between simulators is done using a co-simulation backplane. The co-simulation backplane reads a file describing how the modules are connected, automatically launches the simulators and controls the simulation process. A case study is used as a benchmark to validate the implementation and to evaluate the ...
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design - SBCCI '14, 2014
Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory ... more Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory to cope with transient and permanent faults. This issue is even more relevant in nanotechnologies due to process variability, aging effects, and susceptibility to upsets, among other factors. The literature presents isolated solutions to deal with faults in the MPSoC communication infrastructure. In this context, one gap to be fulfilled is to integrate all layers, resulting in a solution to cope with NoC faults from the physical layer up to the application layer. The goal of this work is to present a runtime integrated approach to cope with NoC faults in MPSoCs. The original contribution is the proposal of a set of hardware and software mechanisms to ensure both efficient and reliable communication in NoC-based MPSoCs. The proposal has an acceptable silicon area overhead and a small memory footprint. Experiments demonstrate that benchmarks (synthetic and real MPSoC applications) were simulated with thousands of random fault injections, and all of them were executed correctly. Moreover, the average application execution time overhead is lower than 0.5%. This suggests the proposed fault tolerant method could be used in applications with reliability and performance constraints.
Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05, 2005
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores th... more This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy consumption. Traffic is seen as an important factor affecting the problem of mapping applications into NoCs having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (SoC). Experiments showed that failing to consider the bit transitions influence on traffic inevitably leads to an energy estimation error. This error is proportional to the amount of bit transitions in transmitted packets. In applications that present a large number of packets exchange, the error is propagated, significantly affecting the mapping results. This paper proposes a high-level application model that captures the traffic effect and uses it to describe the behavior of applications. In order to evaluate the quality of the proposed model, a set of embedded systems were described using both, a previously proposed model (that does not capture the traffic effect), and the model proposed here. Comparing the resulting mappings, those derived from the proposed model showed improvements in energy savings with regard to the other model for all experiments.
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a giv... more ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconfigurable processors suffer from the lack of a pre-established instruction set, making them difficult to program. As intermediate choice, reconfigurable coprocessors systems (RCSs) contain dedicated hardware (coprocessors) coupled to a standard processor core to accelerate specific tasks, allowing inserting or substituting hardware functionalities at ...
New Algorithms, Architectures and Applications for Reconfigurable Computing
Current technology allows building integrated circuits (ICs) complex enough to contain all major ... more Current technology allows building integrated circuits (ICs) complex enough to contain all major elements of a complete end product, which are accordingly called Systems-on-Chip (SoCs)[1]. A SoC usually contains one or more programmable processors, on-chip memory, peripheral devices, and specifically designed complex hardware modules. SoCs are most often implemented as a collection of reusable components named intellectual property cores (IP cores or cores). An IP core is a complex hardware module, created for reuse and that ...
2009 International Symposium on System-on-Chip, 2009
Abstract Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perfo... more Abstract Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a scenario that requires the use of dynamic task mapping. Static mappings have as main advantage the global view of the system, while dynamic mappings normally ...
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Papers by Fernando G . Moraes