Cristina Silvano

A summary of contributions made by significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented. The 27 papers chosen represent those which have most strongly influenced theory and practice in the field.

This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of error control codes (ECC's) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DED-SBD codes with odd-bit-per-byte error correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card.

... Embedded Systems by Vittorio Zaccaria Politecnico di Milano, Italy Mariagiovanna Sami Politecnico di Milano, Italy Donatella Sciuto Politecnico di ... Sold and distributed in North, Central and South America by Kluwer Academic Publishers, 101 Philip Drive, Norwell, MA 02061 ...

Power dissipation in digital circuits is strongly pattern dependent. Thus, to derive accurate simulation-based power estimates, a large amount of input vectors is usually required. This paper proposes a vector compaction technique aiming at providing accurate power figures in a shorter simulation time for complex sequential circuits characterized by some hundreds of inputs. From pair-wise spatio-temporal signal correlations, the proposed

ABSTRACT This special issue of Microprocessors and Microsystems contains extended versions of the best contributions to the Euromicro Digital System Design DSD’2012 Conference, held on September 5th–7th 2012 in Izmir (Turkey). The Euromicro DSD Conference addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers from academia and industry working on state-of-the-art investigations, development and applications. It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multicore infrastructures. The articles presented in this special issue were selected from 185 initial submissions to the DSD’2012 Conference, coming from 41 countries. All the authors of the best paper award candidates and the authors of the best ranked papers were later invited to submit their extended version of the original work for consideration in this special issue. The selected works were revised by the authors, first taking into account feedback obtained in the live discussions at the DSD conference itself, then according to the recommendations given in a number of review iterations of the journal submissions. At the end of the review process, nine articles were selected for publication, which clearly represent the scope of the DSD’2012 conference in those topics related to the ones encountered in MICPRO journal. To better introduce the main topics of this special issue, one invited paper has also been included to open this special issue with an up to date survey on various cross layer techniques and approaches for power, performance, and reliability tradeoffs from the technology, circuit, architecture and application perspectives. The nine selected papers include research works in three main topics: Emerging process technology issues, reliability and variability: The first paper in this group introduces an architecture and detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits. This first paper also demonstrates the suitability of the approach for obtaining accurate radiation failure models. The second paper tackles the impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based model for Bias Temperature Instability (BTI). BTI is one of the most critical degradation mechanisms impacting the device reliability. The third paper proposes a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability taking into consideration the simultaneous variability of the two most critical process parameters, threshold voltage and effective channel length. Fault-tolerant NoC and logic: The first paper presents an energy efficient architecture to provide on-demand fault tolerance to multiple traffic classes running simultaneously on a single network on chip (NoC) platform. To efficiently utilize the vertical bandwidth of Through Silicon Vias (TSVs), the second paper proposes multiplexing several virtual links with dynamically allocated bit rates for guaranteed service connections via a shared TSV-Hub-Array. The TSV-Hub approach is also advantageous under interconnect resilience considerations. Finally, the third paper proposes to exploit logic don’t cares to obtain more compact networks based on SOP expressions. Techniques for multi-core and reconfigurable platforms: The first paper addresses the problem of the automatic two-dimensional data partitioning for DMA transfers on multi-core platforms based on hardware and applications parameters. The second paper introduces a heuristic energy-aware approach for hard real-time systems on cluster-based multi-core platforms. The heuristic algorithm is based on the simulated annealing approach and introduces its online execution making the system adaptive to the run-time changes. The third paper proposed a decentralized control approach for dynamically reconfigurable FPGA systems. The approach is based on distributed modular controllers handling the self-adaptivity of the system reconfigurable regions and a coordinator to respect the system global constraints. Finally, we would like to express our gratitude to the Program Committee of DSD’2012 Conference and to the MICPRO reviewers for their rigorous work in reading and judging these papers: their help and critical insight was invaluable for the selection process of this Special Issue. We would also like to thank the MICPRO Editor-in-Chief, Lech Jozwiak, for agreeing to provide space for this Special Issue and the Elsevier Editorial Office, especially Samyuktha Moorthy, for accompanying us through all steps of the…