To generate test patterns for the complex VLSI designs, an efficient and simple technique is required. This paper present the development of combinational ATPG based on FAN algorithm, testability measures and fault equivalence. The prime... more
To generate test patterns for the complex VLSI designs, an efficient and simple technique is required. This paper present the development of combinational ATPG based on FAN algorithm, testability measures and fault equivalence. The prime aspect of this work is to develop the ATPG algorithm with less number of faults and testability measures. The proposed ATPG algorithm is simple and can be used as an open source for academicians. Analysis on ISCAS 85 circuit along with some basic combinational circuits are present for stuck-at faults.
In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the... more
In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit was used for analysis purpose along with other circuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. The flow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vector data. The algorithm is developed for the test vector compaction and discussed along with results
A disadvantage of double-sampling ΣΔ ADC's is their sensitivity to path mismatch. Recently, an approach to solve this problem was presented. It consists of modifying the noise transfer function (NTF) of the modulator such that it has... more
A disadvantage of double-sampling ΣΔ ADC's is their sensitivity to path mismatch. Recently, an approach to solve this problem was presented. It consists of modifying the noise transfer function (NTF) of the modulator such that it has a zero at the Nyquist frequency, next to those in the baseband. Unfortunately, no systematic design strategy for such ADC's is available. In this work, we present such a strategy. It consists of finding optimal pole positions for the modified NTF. This can be combined with optimizing the zeros of the NTF. Next, we introduce an efficient structure that has enough flexibility to realize the optimized pole positions.
In this paper we discuss design considerations for a sigma-delta modulator (ΣΔM) forming part of a sensor interface for automotive applications. This ΣΔM contains a programmable-gain input interface to accommodate the output signal level... more
In this paper we discuss design considerations for a sigma-delta modulator (ΣΔM) forming part of a sensor interface for automotive applications. This ΣΔM contains a programmable-gain input interface to accommodate the output signal level of a variety of automotive sensors. We show that this characteristic can be efficiently implemented by proper architecture selection and ad hoc sampling and integration capacitor structures. Behavioral simulations of a 17 bit 40 kS/s modulators are included to illustrate the design considerations.
... Engineering, Bangladesh University of Engineering and Technology Dhaka-1 000, Bangladesh e-mail ... pitch period) has receixd interest from different hori-zons of speech analysis-synthesis systems ... noise-free environments but it... more
... Engineering, Bangladesh University of Engineering and Technology Dhaka-1 000, Bangladesh e-mail ... pitch period) has receixd interest from different hori-zons of speech analysis-synthesis systems ... noise-free environments but it fails to yield satisfactory results for noisy speech. ...
In this paper, we compare two different Boolean function reduction methods in order to justify the analytical model of the Monte Carlo data for Boolean function complexity. We use a binary decision diagram (BDD) complexity model (proposed... more
In this paper, we compare two different Boolean function reduction methods in order to justify the analytical model of the Monte Carlo data for Boolean function complexity. We use a binary decision diagram (BDD) complexity model (proposed earlier) and weigh it against the complexity behavior generated by Synopsys Design Compiler (DC). We use this synthesis tool (that utilizes a standard cell library) to generate RTL hardware description of Monte Carlo circuits as gate-level netlists. The two reduction methods (model and DC) transform an arbitrary function into a much-reduced representation of the same function. The comparison confirms that the behavior of Boolean function complexity using the model and the DC is visually and statistically similar; the similarity holds true for BDDs representing functions comprising a wide range of variables and minterms.
This paper describes a general model for static as well as dynamic errors in multibit unit element DAC's. Apart from the static mismatch there are two other error terms arising from switching imperfections. Based on the model, some... more
This paper describes a general model for static as well as dynamic errors in multibit unit element DAC's. Apart from the static mismatch there are two other error terms arising from switching imperfections. Based on the model, some bandpass mismatch shaping techniques are presented. These address both the static mismatch as well as the switch- ing imperfections. The techniques can significantly improve the in band noise.
An efficient iterative algorithm is presented in this paper to design lattice-type perfect reconstruction regular quadrature mirror filters (PR-QMF) by minimizing the pth power of an appropriate error criteria, where p can be a function... more
An efficient iterative algorithm is presented in this paper to design lattice-type perfect reconstruction regular quadrature mirror filters (PR-QMF) by minimizing the pth power of an appropriate error criteria, where p can be a function of ω. The filter bank design is approximated as an unconstrained weighted least squares problem with respect to the lattice coefficients. Typically, only a few
Industry trends aimed at integrating higher levels of circuit functionality have triggered a proliferation of mixed analog-digital systems. Magnified noise coupling through the common chip substrate has made the design and verification of... more
Industry trends aimed at integrating higher levels of circuit functionality have triggered a proliferation of mixed analog-digital systems. Magnified noise coupling through the common chip substrate has made the design and verification of such systems an increasingly difficult task. In this paper we present a new method based on a precorrected-DCT algorithm that extends an eigendecomposition-based technique and can be
To cope with the dynamic workload of actual NoC-based MPSoCs, dynamic mechanisms are required to guarantee the application requirements. Application mapping may drastically influence the system performance and the energy consumption,... more
To cope with the dynamic workload of actual NoC-based MPSoCs, dynamic mechanisms are required to guarantee the application requirements. Application mapping may drastically influence the system performance and the energy consumption, which can be crucial to the success (or failure) of a product, even more for battery-powered embedded systems. In this context, the current work presents an energy-aware dynamic task mapping heuristic, which was evaluated in a real NoC-based MPSoC platform. Results show that the proposed heuristic may reduces up to 22.8% of the communication energy consumption compared to other dynamic mapping heuristics.
ABSTRACT Electrical performances of integrated circuits operating at high frequencies, can be significantly degraded by electrical parasitics non intentionally introduced during the layout design. We present here new tools for the... more
ABSTRACT Electrical performances of integrated circuits operating at high frequencies, can be significantly degraded by electrical parasitics non intentionally introduced during the layout design. We present here new tools for the automatic constraint driven placement and routing of analog integrated circuits. Furthermore we introduce a new constraint generation program, based on AC analysis in the frequency domain. The constraints produced by this program have been-employed to drive the automatic layout tools, during the experiments here reported. These programs automatically produce the layout of high performance integrated circuits, significantly reducing the electrically effective parasitics due to finite length interconnections
Tustin, CA 92680-7022, USA 14351 Myford Rd. MS C-100 ... 1. INTRODUCTION LC two-ports have played an important role in the design of filters [I] because of their very low passband sensitiv-ities to element tolerances. Therefore, in recent... more
Tustin, CA 92680-7022, USA 14351 Myford Rd. MS C-100 ... 1. INTRODUCTION LC two-ports have played an important role in the design of filters [I] because of their very low passband sensitiv-ities to element tolerances. Therefore, in recent years a considerable amount of ...
... (4) I/ K, I/ i X:l(tKO) = XF(tKi) Xzl(tKO) = XS(tKI) TY(tK0) = Tl(tKI) UC(tKO) = (tKi) and they vary in a continuous way between two succesive instants of definition, as it can be seen in Fig.2: ... A UU(Si 4=$ c (s) l-riz-+ Fig.3:... more
... (4) I/ K, I/ i X:l(tKO) = XF(tKi) Xzl(tKO) = XS(tKI) TY(tK0) = Tl(tKI) UC(tKO) = (tKi) and they vary in a continuous way between two succesive instants of definition, as it can be seen in Fig.2: ... A UU(Si 4=$ c (s) l-riz-+ Fig.3: Block-diagram form of DC-DC converter small-signal model. ...
