ATPG

In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit was used for analysis purpose along with other circuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. The flow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vector data. The algorithm is developed for the test vector compaction and discussed along with results

The objective of this paper is to generate a Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of ‘AC-non-redundant fault.’ Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical

Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge.

This research was supported in part by the Semiconductor Research Corporation under contract SRC 95-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new sequential circuit test generator, ALT-TEST, is described which alternates repeatedly between two phases of test generation. The first phase uses a simulation-based genetic algorithm, while the second phase uses

It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply

Abstract. We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vector compaction. Two types of techniques are considered. One is based on the new states a sequential circuit is driven into, and the other is based on the new faults that are detected between consecutive

In this paper a new algorithm named Position Oriented Test Generation (POTG) is proposed which would not only detect whether the chip is faulty or not but, also provide the information regarding the position and the type of fault present. A modified fault dictionary is prepared that is used to minimize the effort in fault location. The proposed algorithm has two parts: first, generation of optimized fault dictionary, and then usage of this fault dictionary. This modified dictionary also gives a heuristic approach to minimize the number of test vectors required for testing the chip with some trade-off with fault coverage. This proposed algorithm is faster in locating a fault in a chip compared to other classical fault location technique. For validation, POTG Algorithm has been applied to ISCAS’85 Benchmark circuit and results have been obtained.

Optimization of testing power is a major signifl- cant task to be carried out in digital circuit design. Low power VLSI circuits dissipate more power dur- ing testing when compared with that of normal op- eration. In this paper a novel method is proposed to reduce the testing power and total energy by reorder- ing the sequence of test vectors