This paper develops an improved approach for hierarchical functional test generation for complex ... more This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generation, hierarchical approaches have been suggested wherein functional constraints are extracted for each module under test (MUT) within a design. These constraints describe a simplified ATPG view for the MUT and thereby speed up the test generation process. This paper develops an improved approach which applies this technique at deeper levels of hierarchy, so that effective tests can be developed for large designs with complex submodules. A tool called FACTOR (FunctionAl ConsTraint extractOR), which implements this methodology is described in this work. Results on the ARM design prove the effectiveness of FACTOR-ising large designs for test generation and testability analysis.
— We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements i... more — We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements in a formal hardware description language providing the semantics of both the functional behavior and timing constraints, and the disciplined use of an SMT solver to analyze speed-path requirements. We are applying our framework for speed-path analysis of several RTL designs from Opencores. I.
This paper develops a novel approach for formally verifying both safety and liveness properties o... more This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped into a monitor circuit with a target fault so that finding a test for the fault corresponds to formally establishing the property. The mapping of the properties to the monitor circuit is described in detail and the process is shown to be sound and complete. Experimental results show that the ATPG-based approach performs better than existing verification techniques, especially for large designs.
... I was also fortunate to have had stimulating discussions with my current and former colleague... more ... I was also fortunate to have had stimulating discussions with my current and former colleagues at CERC and UT: Victor, Karthik, Satish, Kamal, Suresh, Vaibhav, Abhijit, Ravi, Navin, Ramesh, Krishna, Bala, Padmini, Hak-soo, Sungbae, Kyoil, Whitney, and Adam. Special ...
Proceedings International Symposium on Quality Electronic Design, Feb 1, 2002
Abstract With the rapid increase in the functionality of a single chip, the generation of high qu... more Abstract With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the case of ...
This paper develops a novel approach for formally ver- ifying both safety and liveness properties... more This paper develops a novel approach for formally ver- ifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped into a monitor circuit with a target fault so that finding a test for the fault corresponds to formally establish- ing the property. The mapping of the properties to the mon- itor circuit is
2011 12th International Workshop on Microprocessor Test and Verification, 2011
We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements in ... more We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements in a formal hardware description language providing the semantics of both the functional behavior and timing constraints, and the disciplined use of an SMT solver to analyze speed-path requirements. We are applying our framework for speed-path analysis of several RTL designs from Opencores.
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability ... more The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The dynamic power dissi-pated is directly proportional to the switching activity (num-ber of gate outputs that toggles (changes ...
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786), 2000
Abstract The increasing functionality of processor designs has posed a severe challenge for gener... more Abstract The increasing functionality of processor designs has posed a severe challenge for generating high quality manufacturing tests, which can be applied at native speeds. A previous approach was to target one module at a time and extract functional constraints ...
16th International Conference on VLSI Design, 2003. Proceedings., 2003
... SAT versus Sequential ATPG Engines Daniel G. Saab , Jacob A. Abraham and Vivekananda M. V... more ... SAT versus Sequential ATPG Engines Daniel G. Saab , Jacob A. Abraham and Vivekananda M. Vedula Department of Electrical Engineering and Computer Science Case Western Reserve University, Cleveland, Ohio, 44119 saab@eecs.cwru.edu ...
This paper develops an improved approach for hierarchical functional test generation for complex ... more This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generation, hierarchical approaches have been suggested wherein functional constraints are extracted for each module under test (MUT) within a design. These constraints describe a simplified ATPG view for the MUT and thereby speed up the test generation process. This paper develops an improved approach which applies this technique at deeper levels of hierarchy, so that effective tests can be developed for large designs with complex submodules. A tool called FACTOR (FunctionAl ConsTraint extractOR), which implements this methodology is described in this work. Results on the ARM design prove the effectiveness of FACTOR-ising large designs for test generation and testability analysis.
— We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements i... more — We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements in a formal hardware description language providing the semantics of both the functional behavior and timing constraints, and the disciplined use of an SMT solver to analyze speed-path requirements. We are applying our framework for speed-path analysis of several RTL designs from Opencores. I.
This paper develops a novel approach for formally verifying both safety and liveness properties o... more This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped into a monitor circuit with a target fault so that finding a test for the fault corresponds to formally establishing the property. The mapping of the properties to the monitor circuit is described in detail and the process is shown to be sound and complete. Experimental results show that the ATPG-based approach performs better than existing verification techniques, especially for large designs.
... I was also fortunate to have had stimulating discussions with my current and former colleague... more ... I was also fortunate to have had stimulating discussions with my current and former colleagues at CERC and UT: Victor, Karthik, Satish, Kamal, Suresh, Vaibhav, Abhijit, Ravi, Navin, Ramesh, Krishna, Bala, Padmini, Hak-soo, Sungbae, Kyoil, Whitney, and Adam. Special ...
Proceedings International Symposium on Quality Electronic Design, Feb 1, 2002
Abstract With the rapid increase in the functionality of a single chip, the generation of high qu... more Abstract With the rapid increase in the functionality of a single chip, the generation of high quality manufacturing tests which can be applied at-speed has become a serious issue. The problem is further compounded with an increasing level of integration in the case of ...
This paper develops a novel approach for formally ver- ifying both safety and liveness properties... more This paper develops a novel approach for formally ver- ifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped into a monitor circuit with a target fault so that finding a test for the fault corresponds to formally establish- ing the property. The mapping of the properties to the mon- itor circuit is
2011 12th International Workshop on Microprocessor Test and Verification, 2011
We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements in ... more We develop a formal tool for speed-path analysis and debug. We encode speed-path requirements in a formal hardware description language providing the semantics of both the functional behavior and timing constraints, and the disciplined use of an SMT solver to analyze speed-path requirements. We are applying our framework for speed-path analysis of several RTL designs from Opencores.
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability ... more The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The dynamic power dissi-pated is directly proportional to the switching activity (num-ber of gate outputs that toggles (changes ...
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786), 2000
Abstract The increasing functionality of processor designs has posed a severe challenge for gener... more Abstract The increasing functionality of processor designs has posed a severe challenge for generating high quality manufacturing tests, which can be applied at native speeds. A previous approach was to target one module at a time and extract functional constraints ...
16th International Conference on VLSI Design, 2003. Proceedings., 2003
... SAT versus Sequential ATPG Engines Daniel G. Saab , Jacob A. Abraham and Vivekananda M. V... more ... SAT versus Sequential ATPG Engines Daniel G. Saab , Jacob A. Abraham and Vivekananda M. Vedula Department of Electrical Engineering and Computer Science Case Western Reserve University, Cleveland, Ohio, 44119 saab@eecs.cwru.edu ...
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