Shubnikov-deHaas oscillations, cyclotron and maanetonhonon resonance have been studied in heteroj... more Shubnikov-deHaas oscillations, cyclotron and maanetonhonon resonance have been studied in heterojunctions and super-lattices grown with GaxIn1–xAs and InP at the lattice match with x=0.47. A two dimensional electron gas is formed which shows pronounced quantum Hall steps. Cvclotron resonance is observed in the heterojunctions giving m*=0.049mo, with a linewidth which is determined by Gaussian scattering centres. Weakly enhanced q-factors of up to g*=4.6 are observed. The superlattices show an increase in effective mass with decreasing layer thickness, and are shown to be two dimensional u0 to 200 K. Evidence for long range Optical Phonon scattering is presented.
Proceedings Eighth Asian Test Symposium (ATS'99), 1999
This paper describes an approach to minimize the number of test configurations for testing the lo... more This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach is applied to the XILINX SPARTAN, 4000 and 3000 families. On these examples of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then for a single logic cell,
Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 1998
This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs ... more This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Concerning the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the march tests. We also propose a unique test configuration called `pseudo shift register' for mxm arrays of modules. In this configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called `shifted MATS++' is described. Concerning the LUT mode, we use the concept of non-redundant test that proposes to test in LUT mode the parts of the module not tested in RAM mode. Under this hypothesis, it is demonstrated that the test of a single module as well as the test of an mxm array of modules require only 3 test configurations. Using our solution, the test of a complete array of mxm LUT/RAM modules requires 4 test configurations independently of the size of the array and of the modules
The longitudinal and the Hall impedances have been measured as a function of the frequency in a t... more The longitudinal and the Hall impedances have been measured as a function of the frequency in a two-dimensional electron gas at low temperatures. The frequency dependence of the longitudinal impedance can be explained in terms of an equivalent parallel LCR circuit. An effective inductance term arises due to the capacitive coupling between edge states and is shown to scale as 1/nu2 for different filling factors. In the low-frequency range the relative difference between the ac and dc values of the Hall impedance is found to depend quadratically on the frequency and to scale as 1/nu3. These results are shown to be consistent with the existing theoretical model based on the edge-state picture. Finally, the observed symmetry relations when exchanging current contacts or reversing magnetic field are discussed.
ABSTRACT This paper shows how Floating Gate (FG) memory cells behavior during retention tests can... more ABSTRACT This paper shows how Floating Gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provide warning of an impending failure of the memory cell capability to store data. Retention tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress and retention time is established to anticipate retention test results. Moreover, further investigations are made to provide a physical explanation for the correlation. Indeed, it is shown that the same FG memory tunnel oxide traps are activated during electrical stress tests (high electric field) and retention tests (low electric field).
Page 1. A study of the conduction band non-parabolicity, anisotropy and spin splitting in GaAs an... more Page 1. A study of the conduction band non-parabolicity, anisotropy and spin splitting in GaAs and InP This article has been downloaded from IOPscience. Please scroll down to see the full text article. 1987 Semicond. Sci. Technol. 2 568 ...
We have studied the quantum Hall effect in parabolic AlxGa1-xAs and square GaAs quantum wells wit... more We have studied the quantum Hall effect in parabolic AlxGa1-xAs and square GaAs quantum wells with two occupied subbands in magnetic fields B tilted by an angle Theta with respect to the normal to the sample. We built the density-magnetic field ns-B and angle-magnetic field Theta-B topological diagrams for the longitudinal resistivity rhoxx and observed that the latter shows a
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013
ABSTRACT A low-cost auto-calibration technique of Radio-Frequency (RF) Passive Polyphase Filter (... more ABSTRACT A low-cost auto-calibration technique of Radio-Frequency (RF) Passive Polyphase Filter (PPF) for high image rejection in low Intermediate Frequency receiver is presented. The resistance values of the filter are process and temperature dependent with great mismatch constraints especially in the RF domain. That can severely impact the circuit performances if not controlled. In order to overcome this limitation, an in-line auto-calibration of the PPF resistance values, based on Design Of Experiment (DOE) methodology, is presented. Using DOE, a model is derived from thermal and process deviations of the chip responses. This approach results in a robust and low-cost solution.
Shubnikov-deHaas oscillations, cyclotron and maanetonhonon resonance have been studied in heteroj... more Shubnikov-deHaas oscillations, cyclotron and maanetonhonon resonance have been studied in heterojunctions and super-lattices grown with GaxIn1–xAs and InP at the lattice match with x=0.47. A two dimensional electron gas is formed which shows pronounced quantum Hall steps. Cvclotron resonance is observed in the heterojunctions giving m*=0.049mo, with a linewidth which is determined by Gaussian scattering centres. Weakly enhanced q-factors of up to g*=4.6 are observed. The superlattices show an increase in effective mass with decreasing layer thickness, and are shown to be two dimensional u0 to 200 K. Evidence for long range Optical Phonon scattering is presented.
Proceedings Eighth Asian Test Symposium (ATS'99), 1999
This paper describes an approach to minimize the number of test configurations for testing the lo... more This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach is applied to the XILINX SPARTAN, 4000 and 3000 families. On these examples of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then for a single logic cell,
Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 1998
This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs ... more This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Concerning the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the march tests. We also propose a unique test configuration called `pseudo shift register' for mxm arrays of modules. In this configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called `shifted MATS++' is described. Concerning the LUT mode, we use the concept of non-redundant test that proposes to test in LUT mode the parts of the module not tested in RAM mode. Under this hypothesis, it is demonstrated that the test of a single module as well as the test of an mxm array of modules require only 3 test configurations. Using our solution, the test of a complete array of mxm LUT/RAM modules requires 4 test configurations independently of the size of the array and of the modules
The longitudinal and the Hall impedances have been measured as a function of the frequency in a t... more The longitudinal and the Hall impedances have been measured as a function of the frequency in a two-dimensional electron gas at low temperatures. The frequency dependence of the longitudinal impedance can be explained in terms of an equivalent parallel LCR circuit. An effective inductance term arises due to the capacitive coupling between edge states and is shown to scale as 1/nu2 for different filling factors. In the low-frequency range the relative difference between the ac and dc values of the Hall impedance is found to depend quadratically on the frequency and to scale as 1/nu3. These results are shown to be consistent with the existing theoretical model based on the edge-state picture. Finally, the observed symmetry relations when exchanging current contacts or reversing magnetic field are discussed.
ABSTRACT This paper shows how Floating Gate (FG) memory cells behavior during retention tests can... more ABSTRACT This paper shows how Floating Gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provide warning of an impending failure of the memory cell capability to store data. Retention tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress and retention time is established to anticipate retention test results. Moreover, further investigations are made to provide a physical explanation for the correlation. Indeed, it is shown that the same FG memory tunnel oxide traps are activated during electrical stress tests (high electric field) and retention tests (low electric field).
Page 1. A study of the conduction band non-parabolicity, anisotropy and spin splitting in GaAs an... more Page 1. A study of the conduction band non-parabolicity, anisotropy and spin splitting in GaAs and InP This article has been downloaded from IOPscience. Please scroll down to see the full text article. 1987 Semicond. Sci. Technol. 2 568 ...
We have studied the quantum Hall effect in parabolic AlxGa1-xAs and square GaAs quantum wells wit... more We have studied the quantum Hall effect in parabolic AlxGa1-xAs and square GaAs quantum wells with two occupied subbands in magnetic fields B tilted by an angle Theta with respect to the normal to the sample. We built the density-magnetic field ns-B and angle-magnetic field Theta-B topological diagrams for the longitudinal resistivity rhoxx and observed that the latter shows a
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013
ABSTRACT A low-cost auto-calibration technique of Radio-Frequency (RF) Passive Polyphase Filter (... more ABSTRACT A low-cost auto-calibration technique of Radio-Frequency (RF) Passive Polyphase Filter (PPF) for high image rejection in low Intermediate Frequency receiver is presented. The resistance values of the filter are process and temperature dependent with great mismatch constraints especially in the RF domain. That can severely impact the circuit performances if not controlled. In order to overcome this limitation, an in-line auto-calibration of the PPF resistance values, based on Design Of Experiment (DOE) methodology, is presented. Using DOE, a model is derived from thermal and process deviations of the chip responses. This approach results in a robust and low-cost solution.
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