ATPG

It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply

Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge.

In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit was used for analysis purpose along with other circuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. The flow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vector data. The algorithm is developed for the test vector compaction and discussed along with results

The impact of the recent exponential increase incomplexity of digital VLSI circuits has heavily affectedverification  methodologies.  Many  advances towardverification  and  debugging techniques  of  digital  VLSI  circuitshave  relied  onComputer  Aided  Design  (CAD). Existing techniques are highly dependenton specializedtest patterns with specific numbersincreased bytherising  complexity  ofVLSIcircuits. A  second  problem arises  in  the  form  oflarge  sizesof injecting circuitsfor correction andlarge number of SAT solver calls witha negative impact on theresultantrunning  time.Three  goals  arise:  first,  diminishingdependenceona  given  test pattern  by  incrementally  generating  compact  test  patterns  corresponding  to  design errorsduring the rectificationprocess. Second,  to reduce the  size  of  in-circuit  mutation  circuit for error-fixing  process.Finally,distribution  of  test  patterns  can  be performedin  parallel with a positive  impact  on  digital  VLSI  circuitswith  large  numbersof  inputs  and  outputs.The experimental results illustrate that the proposed incremental correction algorithm can fix design bugs  of  type  gate  replacements  in  several  digital  VLSI circuits from  ISCAS'85  with  high  speed and  full  accuracy.The  speedof proposed  Auto-correctionmechanismoutperforms  the  latest existing  methodsaround  4.8xusing ISCAS'85  benchmarks.The  parallel  distribution  of  test patterns  on  digital  VLSI  circuits  during  generating  new  compact  test  patterns  achieves  speed around 1.2x compared to latest methods.