Defects and hence faults are present in the QCA (Quantum-dot Cellular Automata) nanotechnology de... more Defects and hence faults are present in the QCA (Quantum-dot Cellular Automata) nanotechnology devices and circuits. Hence it is important to test these nanotechnology devices and circuits. This paper investigates the new properties for the test generation for the QCA device majority voter. A method of test generation is developed to find the single missing input cell deposition defects in the QCA majority voter using the proposed properties. The generated test vectors are verified using algebraic method. The generated test vectors are mapped at the QCA layout level to validate capability to detect the single input missing cell deposition defect.
To generate test patterns for the complex VLSI designs, an efficient and simple technique is requ... more To generate test patterns for the complex VLSI designs, an efficient and simple technique is required. This paper present the development of combinational ATPG based on FAN algorithm, testability measures and fault equivalence. The prime aspect of this work is to develop the ATPG algorithm with less number of faults and testability measures. The proposed ATPG algorithm is simple and can be used as an open source for academicians. Analysis on ISCAS 85 circuit along with some basic combinational circuits are present for stuck-at faults.
Defects and hence faults are present in the QCA (Quantum-dot Cellular Automata) nanotechnology de... more Defects and hence faults are present in the QCA (Quantum-dot Cellular Automata) nanotechnology devices and circuits. Hence it is important to test these nanotechnology devices and circuits. This paper investigates the new properties for the test generation for the QCA device majority voter. A method of test generation is developed to find the single missing input cell deposition defects in the QCA majority voter using the proposed properties. The generated test vectors are verified using algebraic method. The generated test vectors are mapped at the QCA layout level to validate capability to detect the single input missing cell deposition defect.
To generate test patterns for the complex VLSI designs, an efficient and simple technique is requ... more To generate test patterns for the complex VLSI designs, an efficient and simple technique is required. This paper present the development of combinational ATPG based on FAN algorithm, testability measures and fault equivalence. The prime aspect of this work is to develop the ATPG algorithm with less number of faults and testability measures. The proposed ATPG algorithm is simple and can be used as an open source for academicians. Analysis on ISCAS 85 circuit along with some basic combinational circuits are present for stuck-at faults.
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Papers by Vaishali Dhare