— This paper reports on the design, implementation, and test of a stimulation back-end, for an im... more — This paper reports on the design, implementation, and test of a stimulation back-end, for an implantable retinal prosthesis. In addition to traditional rectangular pulse shapes, the circuit features biphasic stimulation pulses with both rising and falling exponential shapes, whose time constants are digitally programmable. A class-B second generation current conveyor is used as a wide-swing, high-output-resistance stimulation current driver, delivering stimulation current pulses of up to ±96 µA to the target tissue. Duration of the generated current pulses is programmable within the range of 100 µs to 3 ms. Current-mode digital-to-analog converters (DACs) are used to program the amplitudes of the stimulation pulses. Fabricated using the IBM 130 nm process, the circuit consumes 1.5´1.5 mm 2 of silicon area. According to the measurements, the DACs exhibit DNL and INL of 0.23 LSB and 0.364 LSB, respectively. Experimental results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance of as high as 25 kΩ. Maximum power consumption of the proposed design is 3.4 mW when delivering biphasic rectangular pulses to the target load. A charge pump block is in charge of the upconversion of the standard 1.2-V supply voltage to ±3.3V.
Millions of patients are either slowly losing their vision or are already blind due to retinal de... more Millions of patients are either slowly losing their vision or are already blind due to retinal degenerative diseases such as retinitis pigmentosa (RP) and age‑related macular degeneration (AMD) or because of accidents or injuries. Employment of artificial means to treat extreme vision impairment has come closer to reality during the past few decades. Currently, many research groups work towards effective solutions to restore a rudimentary sense of vision to the blind. Aside from the efforts being put on replacing damaged parts of the retina by engineered living tissues or microfabricated photoreceptor arrays, implantable electronic microsystems, referred to as visual prostheses, are also sought as promising solutions to restore vision. From a functional point of view, visual prostheses receive image information from the outside world and deliver them to the natural visual system, enabling the subject to receive a meaningful perception of the image. This paper provides an overview of technical design aspects and clinical test results of visual prostheses, highlights past and recent progress in realizing chronic high‑resolution visual implants as well as some technical challenges confronted when trying to enhance the functional quality of such devices.
This paper reports a novel high-compliance, very accurate and ultra-high output resistance curren... more This paper reports a novel high-compliance, very accurate and ultra-high output resistance current mirror. These features are achieved by employing a combination of negative and positive feedbacks in the proposed circuit. This makes the proposed current mirror unique in gathering ultra-high output resistance, high compliance, and high accuracy ever demanded merits. The principle of operation of this structure is discussed, its main formulas are derived and its outstanding performance is verified by Cadence post-layout simulations. Designed in the IBM 130-nm standard CMOS process, the circuit consumes 230110 µm2 of silicon area. Post-layout simulation results indicate that with a 3.3-V power supply, output voltage compliance of 0.93VSupply is achieved at a maximum output current of 96 µA. Moreover, an extremely ultra-high output resistance of 320 GΩ is achieved, which is one of the highest values of output resistance for current mirrors implemented reported using regular CMOS technology. The -3 dB upper cut-off frequency of the proposed circuit is 100 MHz and the output/input current transfer error is 0.1%. The whole circuit, including bias circuitry, consumes 0.57 mW when delivering 96 µA to the load.
This paper reports an energy-efficient waveform generator, dedicated to implantable retinal micro... more This paper reports an energy-efficient waveform generator, dedicated to implantable retinal microstimulators. The circuit features flexible current-mode stimuli such as rising and falling exponential pulses in addition to rectangular pulses. In order to apply the stimulation current to the electrode at the defined current levels (±96µA) and with sufficient voltage headroom (±3V), a class AB second generation current conveyor is designed as the output stage. To up-convert the 1.2-V supply voltage to ±3.3V, the output stage is equipped with an on-chip electrode-tissue driver. Duration of the generated current pulses is programmable within the range of 100µs to 3ms. Current-steering DACs are used to set the amplitudes of pulses. They exhibit DNL and INL of 0.04 and 0.17LSB, respectively. The amplitude, duration, and time constant of exponential pulses are independently programmable. Designed in the IBM in 130nm process, the circuit consumes 1.51.5 mm2 of silicon area. Post-layout simulation results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance as high as 30kΩ. The proposed design consumes a maximum of 1.2mW in the rectangular pulse mode.
This paper introduces a noncoherent low-power BPSK demodulator and clock recovery circuit for wir... more This paper introduces a noncoherent low-power BPSK demodulator and clock recovery circuit for wirelessly-powered biomedical implants. The received data are detected using a pulse width measurement technique, which is based on complementary analog voltage slopes generated by charging two capacitors with constant currents. In addition to low power consumption and simple circuit implementation, the proposed demodulator exhibits a data-rate-to-carrier-frequency ratio of as high as 100%. Therefore, the proposed demodulator is especially appropriate for implantable biomedical devices such as visual prostheses, where high-speed data transfer is of crucial importance. The circuit is designed and simulated in a standard 0.18-µm CMOS process and occupies 50×70 µm2 of silicon area. Operated using a 1.8-V supply voltage, the proposed demodulator and clock recovery circuit consumes 77.9µW at a data rate of 10Mbps. Experimental results of a proof-of-concept prototype also support the proposed idea.
In this paper, two new hybrid CT/DT cascade ΣΔ modulators are proposed for use in low-voltage bro... more In this paper, two new hybrid CT/DT cascade ΣΔ modulators are proposed for use in low-voltage broadband applications. Unlike the MASH architecture, these modulators are less sensitive to amplifier DC gain of continuous-time (CT) stage and avoid the need of compensation for finite gain-bandwidth induced error in CT loop filter. The modulators also feature global resonation scheme, noise transfer function enhancement, double-sampling technique and flat and unity STFs. These techniques are combined together in novel topologies that allow increasing the resolution in nanometer CMOS high-speed applications. Behavioral simulations confirm the effectiveness of the proposed schemes.
Geometric programming (GP) has been employed in automatic design of analog integrated circuits. I... more Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of the initial equations and the parameters used in these equations. This, in circuit design, causes discrepancies between GP predictions and simulation results-especially in sub-micron devices-thus resulting in a non-globally optimum circuit design. In this paper, two major sources of this discrepancy are introduced and resolved by an iterative simulation-equation-based design methodology based on GP for operational amplifiers. In order to show the effectiveness of the methodology, it has been applied to two op-amp architectures.
This paper presents a novel hybrid continuous-time (CT) and discrete-time (DT) sturdy multi-stage... more This paper presents a novel hybrid continuous-time (CT) and discrete-time (DT) sturdy multi-stage noise shaping (SMASH) ΣΔ modulator architecture. The double-sampling technique is employed in the DT second stage modulator to reduce the power consumption of the overall modulator. A flat and unity STFs are used in the first and second stage modulators, respectively, to reduce the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first stage CT modulator. As a design example, the proposed SMASH 2-2 modulator is designed in a 90 nm CMOS technology with 1 V power supply. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 80.4 dB in 12.5 MHz bandwidth with 17 mW power consumption while operating at 200 MHz sampling frequency.
This paper describes a low-power fully integrated CMOS low-pass filter with extremely low cut-off... more This paper describes a low-power fully integrated CMOS low-pass filter with extremely low cut-off frequency range for use in implantable biomedical applications. The filter takes advantage of system-level properties of applying indirect negative feedback on an OTA to realize a low-cut-off frequency. It also features active capacitance multiplication using a second-generation current conveyor. Both of these techniques help reduce the silicon area of the proposed low-pass filter. Based on the proposed idea, a 1st-order low-pass Gm-C filter was designed in a 0.5-μm standard CMOS process, occupying a core area of 0.0048mm2. Cut-off frequency of the filter is tunable from 0.75Hz to 9.4Hz. Operated with ±1.5V supply voltages, power consumption of the filter ranges from 50nW to 740nW.
As the sampling frequency in modulators is upper limited by the amplifier bandwidth and power con... more As the sampling frequency in modulators is upper limited by the amplifier bandwidth and power consumption, sigma-delta modulators should operate with low oversampling ratios (OSRs) in broadband applications. But, the modulator accuracy is reduced by lowering the OSR. Multirate signal processing and double-sampling have been proven appropriate techniques for preventing this effect and also lowering the power consumption in discrete-time modulators. In this paper, both of these techniques are simultaneously used to achieve power efficient hybrid CT/DT sigma-delta modulators.
— This paper reports on the design, implementation, and test of a stimulation back-end, for an im... more — This paper reports on the design, implementation, and test of a stimulation back-end, for an implantable retinal prosthesis. In addition to traditional rectangular pulse shapes, the circuit features biphasic stimulation pulses with both rising and falling exponential shapes, whose time constants are digitally programmable. A class-B second generation current conveyor is used as a wide-swing, high-output-resistance stimulation current driver, delivering stimulation current pulses of up to ±96 µA to the target tissue. Duration of the generated current pulses is programmable within the range of 100 µs to 3 ms. Current-mode digital-to-analog converters (DACs) are used to program the amplitudes of the stimulation pulses. Fabricated using the IBM 130 nm process, the circuit consumes 1.5´1.5 mm 2 of silicon area. According to the measurements, the DACs exhibit DNL and INL of 0.23 LSB and 0.364 LSB, respectively. Experimental results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance of as high as 25 kΩ. Maximum power consumption of the proposed design is 3.4 mW when delivering biphasic rectangular pulses to the target load. A charge pump block is in charge of the upconversion of the standard 1.2-V supply voltage to ±3.3V.
Millions of patients are either slowly losing their vision or are already blind due to retinal de... more Millions of patients are either slowly losing their vision or are already blind due to retinal degenerative diseases such as retinitis pigmentosa (RP) and age‑related macular degeneration (AMD) or because of accidents or injuries. Employment of artificial means to treat extreme vision impairment has come closer to reality during the past few decades. Currently, many research groups work towards effective solutions to restore a rudimentary sense of vision to the blind. Aside from the efforts being put on replacing damaged parts of the retina by engineered living tissues or microfabricated photoreceptor arrays, implantable electronic microsystems, referred to as visual prostheses, are also sought as promising solutions to restore vision. From a functional point of view, visual prostheses receive image information from the outside world and deliver them to the natural visual system, enabling the subject to receive a meaningful perception of the image. This paper provides an overview of technical design aspects and clinical test results of visual prostheses, highlights past and recent progress in realizing chronic high‑resolution visual implants as well as some technical challenges confronted when trying to enhance the functional quality of such devices.
This paper reports a novel high-compliance, very accurate and ultra-high output resistance curren... more This paper reports a novel high-compliance, very accurate and ultra-high output resistance current mirror. These features are achieved by employing a combination of negative and positive feedbacks in the proposed circuit. This makes the proposed current mirror unique in gathering ultra-high output resistance, high compliance, and high accuracy ever demanded merits. The principle of operation of this structure is discussed, its main formulas are derived and its outstanding performance is verified by Cadence post-layout simulations. Designed in the IBM 130-nm standard CMOS process, the circuit consumes 230110 µm2 of silicon area. Post-layout simulation results indicate that with a 3.3-V power supply, output voltage compliance of 0.93VSupply is achieved at a maximum output current of 96 µA. Moreover, an extremely ultra-high output resistance of 320 GΩ is achieved, which is one of the highest values of output resistance for current mirrors implemented reported using regular CMOS technology. The -3 dB upper cut-off frequency of the proposed circuit is 100 MHz and the output/input current transfer error is 0.1%. The whole circuit, including bias circuitry, consumes 0.57 mW when delivering 96 µA to the load.
This paper reports an energy-efficient waveform generator, dedicated to implantable retinal micro... more This paper reports an energy-efficient waveform generator, dedicated to implantable retinal microstimulators. The circuit features flexible current-mode stimuli such as rising and falling exponential pulses in addition to rectangular pulses. In order to apply the stimulation current to the electrode at the defined current levels (±96µA) and with sufficient voltage headroom (±3V), a class AB second generation current conveyor is designed as the output stage. To up-convert the 1.2-V supply voltage to ±3.3V, the output stage is equipped with an on-chip electrode-tissue driver. Duration of the generated current pulses is programmable within the range of 100µs to 3ms. Current-steering DACs are used to set the amplitudes of pulses. They exhibit DNL and INL of 0.04 and 0.17LSB, respectively. The amplitude, duration, and time constant of exponential pulses are independently programmable. Designed in the IBM in 130nm process, the circuit consumes 1.51.5 mm2 of silicon area. Post-layout simulation results indicate that the stimuli generator meets expected requirements when connected to electrode-tissue impedance as high as 30kΩ. The proposed design consumes a maximum of 1.2mW in the rectangular pulse mode.
This paper introduces a noncoherent low-power BPSK demodulator and clock recovery circuit for wir... more This paper introduces a noncoherent low-power BPSK demodulator and clock recovery circuit for wirelessly-powered biomedical implants. The received data are detected using a pulse width measurement technique, which is based on complementary analog voltage slopes generated by charging two capacitors with constant currents. In addition to low power consumption and simple circuit implementation, the proposed demodulator exhibits a data-rate-to-carrier-frequency ratio of as high as 100%. Therefore, the proposed demodulator is especially appropriate for implantable biomedical devices such as visual prostheses, where high-speed data transfer is of crucial importance. The circuit is designed and simulated in a standard 0.18-µm CMOS process and occupies 50×70 µm2 of silicon area. Operated using a 1.8-V supply voltage, the proposed demodulator and clock recovery circuit consumes 77.9µW at a data rate of 10Mbps. Experimental results of a proof-of-concept prototype also support the proposed idea.
In this paper, two new hybrid CT/DT cascade ΣΔ modulators are proposed for use in low-voltage bro... more In this paper, two new hybrid CT/DT cascade ΣΔ modulators are proposed for use in low-voltage broadband applications. Unlike the MASH architecture, these modulators are less sensitive to amplifier DC gain of continuous-time (CT) stage and avoid the need of compensation for finite gain-bandwidth induced error in CT loop filter. The modulators also feature global resonation scheme, noise transfer function enhancement, double-sampling technique and flat and unity STFs. These techniques are combined together in novel topologies that allow increasing the resolution in nanometer CMOS high-speed applications. Behavioral simulations confirm the effectiveness of the proposed schemes.
Geometric programming (GP) has been employed in automatic design of analog integrated circuits. I... more Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of the initial equations and the parameters used in these equations. This, in circuit design, causes discrepancies between GP predictions and simulation results-especially in sub-micron devices-thus resulting in a non-globally optimum circuit design. In this paper, two major sources of this discrepancy are introduced and resolved by an iterative simulation-equation-based design methodology based on GP for operational amplifiers. In order to show the effectiveness of the methodology, it has been applied to two op-amp architectures.
This paper presents a novel hybrid continuous-time (CT) and discrete-time (DT) sturdy multi-stage... more This paper presents a novel hybrid continuous-time (CT) and discrete-time (DT) sturdy multi-stage noise shaping (SMASH) ΣΔ modulator architecture. The double-sampling technique is employed in the DT second stage modulator to reduce the power consumption of the overall modulator. A flat and unity STFs are used in the first and second stage modulators, respectively, to reduce the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first stage CT modulator. As a design example, the proposed SMASH 2-2 modulator is designed in a 90 nm CMOS technology with 1 V power supply. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 80.4 dB in 12.5 MHz bandwidth with 17 mW power consumption while operating at 200 MHz sampling frequency.
This paper describes a low-power fully integrated CMOS low-pass filter with extremely low cut-off... more This paper describes a low-power fully integrated CMOS low-pass filter with extremely low cut-off frequency range for use in implantable biomedical applications. The filter takes advantage of system-level properties of applying indirect negative feedback on an OTA to realize a low-cut-off frequency. It also features active capacitance multiplication using a second-generation current conveyor. Both of these techniques help reduce the silicon area of the proposed low-pass filter. Based on the proposed idea, a 1st-order low-pass Gm-C filter was designed in a 0.5-μm standard CMOS process, occupying a core area of 0.0048mm2. Cut-off frequency of the filter is tunable from 0.75Hz to 9.4Hz. Operated with ±1.5V supply voltages, power consumption of the filter ranges from 50nW to 740nW.
As the sampling frequency in modulators is upper limited by the amplifier bandwidth and power con... more As the sampling frequency in modulators is upper limited by the amplifier bandwidth and power consumption, sigma-delta modulators should operate with low oversampling ratios (OSRs) in broadband applications. But, the modulator accuracy is reduced by lowering the OSR. Multirate signal processing and double-sampling have been proven appropriate techniques for preventing this effect and also lowering the power consumption in discrete-time modulators. In this paper, both of these techniques are simultaneously used to achieve power efficient hybrid CT/DT sigma-delta modulators.
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