The authors report how self-aligned pnp devices with basewidths close to 50 nm have been fabricated using a preamorphizing Ge implant prior to the As base implant. They investigated the sensitivity of pnp performance to collector epi... more
The authors report how self-aligned pnp devices with basewidths close to 50 nm have been fabricated using a preamorphizing Ge implant prior to the As base implant. They investigated the sensitivity of pnp performance to collector epi thickness, base width and the energy of the base implant, culminating in the achievement of devices with f T as high as 38 GHz. ECL (emitter coupled logic) ring oscillators built with these pnp devices have delays as small as 35 ps per stage, demonstrating that the device parasitics have been successfully minimized. Both the fT of 38 GHz and the 35 ps ECL delay represent new records for pnp devices, showing a performance level comparable to that of current high-performance npn technologies
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ABSTRACT
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The advent of low temperature epitaxy processes provides a new degree of freedom for bipolar device scaling. This paper describes new vertical scaling concepts and process technology elements required for advanced scaled bipolar (NPN and... more
The advent of low temperature epitaxy processes provides a new degree of freedom for bipolar device scaling. This paper describes new vertical scaling concepts and process technology elements required for advanced scaled bipolar (NPN and PNP) devices which will be the core of high-performance application-specific bipolar, BiCMOS, or complementary bipolar/BiCMOS logic and memory chips. In particular, the authors address key
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A two-dimensional device simulator is used to examine the various low-temperature profile design strategies for silicon bipolar transistors. It is found that a relaxed scaling approach offers the best overall results for high speed... more
A two-dimensional device simulator is used to examine the various low-temperature profile design strategies for silicon bipolar transistors. It is found that a relaxed scaling approach offers the best overall results for high speed circuit operation at liquid nitrogen (LN 2) temperatures. To support these calculations, experimental results which demonstrate that sub-100-ps emitter-coupled-logic circuit (ECL) operation at LN2 temperature is
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This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper... more
This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above challenges. A CELL processor consists of a
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We have performed a high-statistics measurement of Bhabha scattering and of the production of hadrons in electron-positron annihilation at PETRA energies (12 GeV<~sqrt[s]<~36.7 GeV). Combining the results... more
We have performed a high-statistics measurement of Bhabha scattering and of the production of hadrons in electron-positron annihilation at PETRA energies (12 GeV<~sqrt[s]<~36.7 GeV). Combining the results with measurements of μ + μ - and τ + τ - production enables ...
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... DD Awschalom, J. Warnock, J. M. Hong, LL Chang, M. B.Ketchen, and W. J. Gallagher ... Unlike the electronic dynamics, the time-resolved behavior of this magnetization was found to be ... netic response is noticeably altered by... more
... DD Awschalom, J. Warnock, J. M. Hong, LL Chang, M. B.Ketchen, and W. J. Gallagher ... Unlike the electronic dynamics, the time-resolved behavior of this magnetization was found to be ... netic response is noticeably altered by quantum-size affects, leading to clear peaks in the ...
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Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25-μm bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size.... more
Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25-μm bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25-μm-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA
We present a magneto-optical study of ZnSe/Zn{sub 1-x-y}CdâMn{sub y}Se quantum-well structures in which a suitable choice of the Cd composition leads to a system that is type I at zero magnetic field. When a magnetic field is applied... more
We present a magneto-optical study of ZnSe/Zn{sub 1-x-y}CdâMn{sub y}Se quantum-well structures in which a suitable choice of the Cd composition leads to a system that is type I at zero magnetic field. When a magnetic field is applied perpendicular to the layers of the structure, the band edges split in such a way as to make the upper {bold Ï}â (1/2, t 3/2) exciton transition type II, while the ground state {bold Ï}{sub +} (-1/2, -3/2) exciton component remains type I at all field values. This alignment reduces the probability for carrier relaxation from the higher-energy exciton component and opens the possibility of hole-spin population inversion via optical pumping. {copyright} {ital 1997} {ital The American Physical Society}
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Abstract The authors have developed a planar, self-aligned, epitaxial Si or SiGe-base bipolar technology and explored intrinsic profile design leverage for high-performance devices in three distinct areas: transit time reduction,... more
Abstract The authors have developed a planar, self-aligned, epitaxial Si or SiGe-base bipolar technology and explored intrinsic profile design leverage for high-performance devices in three distinct areas: transit time reduction, collector-base (CB) junction ...
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A self-aligned epitaxial base technology is presented which allows fabrication of advanced bipolar devices with 40 to 60 nm basewidths and implementation of novel profile design concepts. The viability of this technology for advanced... more
A self-aligned epitaxial base technology is presented which allows fabrication of advanced bipolar devices with 40 to 60 nm basewidths and implementation of novel profile design concepts. The viability of this technology for advanced bipolar circuits has been examined by fabricating ECL ring oscillators, thus demonstrating that fully scaled epi-base devices can be successfully integrated. Devices with current gains of
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In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the... more
In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the deep and shallow trench isolation processes. Next are the npn collector reach-through and anneal, CMOS well and threshold implants,
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Abstract An ECL (emitter coupled logic) circuit with an AC-coupled active pull-down emitter follower configuration is described. An unloaded ring oscillator gate delay of 13.2 ps has been achieved at 6.2 mW, in a 50 GHz-f T ion-implanted... more
Abstract An ECL (emitter coupled logic) circuit with an AC-coupled active pull-down emitter follower configuration is described. An unloaded ring oscillator gate delay of 13.2 ps has been achieved at 6.2 mW, in a 50 GHz-f T ion-implanted silicon bipolar technology. This ...
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Technology scaling has provided the semiconductor industry a recipe to successfully meet the application demands for performance for over three decades. This computational capacity was further fueled by the success of circuit and... more
Technology scaling has provided the semiconductor industry a recipe to successfully meet the application demands for performance for over three decades. This computational capacity was further fueled by the success of circuit and architecture-level innovation, which provided performance improvement in each processor generation. However, future processor designs face a number of key challenges in sustaining the growth trends. The dawn of the 22nm node, and beyond, marks an era of new trends and challenges; where the cost and complexity associated with each technology node is increasing at much faster rate than the device performance gains. Novel tools and design methodologies are needed to not only compensate for these challenges but also to leverage emerging technologies to achieve the desired performance in future processor architectures. Technology alternatives such as D integration have attracted significant interest as an additional way of sustaining the density scaling and performance growth. D integration provides some unique benefits for processor design, such as packaging density, interconnect bandwidth and latency, modularity, and heterogeneity. Packaging density improvement provided by 3D can be used to continue improvements in processing and storage capacity as well as enabling a gradual shift towards integrating the full system in one stack. Through-Silicon-Vias (TSVs) provide lower latency and higher bandwidth that improves interconnect-limited performance. 3D enables modular design of a variety of systems from a shared set of sub-components through functional separation of the device layers. As a result, different layers can be independently manufactured in the most cost effective ways, which can be stacked to compose a wide range of customized systems. Optimizing layer interfaces and infrastructure components, such as power delivery and clocking, can further enhance the inherent modularity advantages. 3D provides opportunities for composing future systems by integrating disparate technologies as well as different technology generations in the same stack. It can be used to incorporate a wide range of device layers including non-volatile memory layers, MEMS, FPGAs, DRAM or photonics in the same stack, easing the IO/off-chip bandwidth limitations. This provides the opportunity to enable processor architectures with new computation, storage and communication capabilities. The system-level benefits of 3D will be determined, to a significant degree, by the effectiveness of novel design methodologies that explore the new design space introduced by the vertical dimension. Design flow optimization is essential in achieving the highest performance gains as well as tackling the more prominent interdependencies among performance, power dissipation, temperatures, interconnectivity and reliability in 3D. This presentation will highlight these challenges and opportunities.
Research Interests: Continuous Improvement, TSV, CAD, Performance Evaluation, Processor Architecture, and 12 morePerformance Improvement, Design Methodology, Cost effectiveness, Non-Volatile Memory Technologies, Chip, Emerging Technology, Three Dimensional, DESIGN SPACE, Electronics Packaging, Bandwidth, Modular Design, and Power Dissipation
Abstract The IBM zEnterprise z196 processor chip is an energy efficient high-frequency, high-performance design that implements 4 processor cores optimized for maximum single-thread performance. Chip energy efficiency is improved by 25%... more
Abstract The IBM zEnterprise z196 processor chip is an energy efficient high-frequency, high-performance design that implements 4 processor cores optimized for maximum single-thread performance. Chip energy efficiency is improved by 25% compared to the previous ...
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ABSTRACT
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... Other noted high-speed design points in the 90nm tech-nology are the single precision [2] and low FO4 double-precision [3] multipliers. The first cycle starts with Radix-4 Booth logic whose inputs are two 53b operands. ... ISSCC 2005... more
... Other noted high-speed design points in the 90nm tech-nology are the single precision [2] and low FO4 double-precision [3] multipliers. The first cycle starts with Radix-4 Booth logic whose inputs are two 53b operands. ... ISSCC 2005 / February 9, 2005 / Salon 1-6 / 9:30 AM ...
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A microprocessor implementing IBM S/390 archi- tecture operates in a 10 2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2- m CMOS technology with five layers of metal and tungsten local interconnect. The... more
A microprocessor implementing IBM S/390 archi- tecture operates in a 10 2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2- m CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm 17.30 mm with about 7.8 million transistors. The power supply is 2.5 V
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Data from the MARK-J detector on the reactions e + e - →μ + μ - , τ + τ - in the center-of-mass energy range from 12 to 36.7 GeV are presented. The μ, τ radii are shown to be <10 -16 cm. A search has been made for the production of a... more
Data from the MARK-J detector on the reactions e + e - →μ + μ - , τ + τ - in the center-of-mass energy range from 12 to 36.7 GeV are presented. The μ, τ radii are shown to be <10 -16 cm. A search has been made for the production of a new heavy lepton and for the production ...
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... James Warnock1, Leon Sigal2, Dieter Wendel3, K Paul Muller4, Joshua Friedrich5, Victor Zyuban2, Ethan Cannon6, AJ KleinOsowski6 ... This paper will focus on the special features added to the CSE design with these considerations in... more
... James Warnock1, Leon Sigal2, Dieter Wendel3, K Paul Muller4, Joshua Friedrich5, Victor Zyuban2, Ethan Cannon6, AJ KleinOsowski6 ... This paper will focus on the special features added to the CSE design with these considerations in mind. ...
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A two-dimensional device simulator was used to examine the various profile design strategies for silicon bipolar transistors operating at liquid-nitrogen temperatures. Special emphasis was placed on the scaling tradeoffs of these design... more
A two-dimensional device simulator was used to examine the various profile design strategies for silicon bipolar transistors operating at liquid-nitrogen temperatures. Special emphasis was placed on the scaling tradeoffs of these design approaches. It is concluded that a relaxed scaling technique based on the maintenance of constant base Gummel number with a slight decrease in emitter doping level probably offers
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Abstract An emitter-coupled logic (ECL) gate with an AC-coupled active pull-down emitter-follower stage that gives high speed at lower power is described. Significant reduction of the speed-power product can be achieved over the... more
Abstract An emitter-coupled logic (ECL) gate with an AC-coupled active pull-down emitter-follower stage that gives high speed at lower power is described. Significant reduction of the speed-power product can be achieved over the conventional ECL gate. The speed/power ...
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ABSTRACT This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed... more
ABSTRACT This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm die, employing 1.2B transistors in a 45 nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 m DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning.