We have developed a novel analog front-end part of a wireless brain oxymeter receiver instrument ... more We have developed a novel analog front-end part of a wireless brain oxymeter receiver instrument based on near-infrared spectroreflectometry (NIRS). The NIRS receiver makes use of dynamic threshold transistors (DTMOS) for low voltage (1–V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs are in a class AB configuration, and uses DTMOS devices for input common-mode range enhancement. Post-layout simulations under a 5 pF load, using 0.18 µm CMOS technology results are, for the OTA, an input referred noise of 134 nV/√Hz at 1 kHz, and a power consumption of 16.7 µW without any extra noise reduction technique. Also, the TIA gives 208 pA/√Hz at 1 kHz, while having a power consumption of only 10.9 µW. The proposed analog front-end circuits have been used to implement a NIRS receiver instrument with improved ultra low-light level measurements, high resolution...
In this work, a very robust quadrature time-domain CMOS front-end for transform-domain UWB WLAN r... more In this work, a very robust quadrature time-domain CMOS front-end for transform-domain UWB WLAN receiver has been presented, showing 1-dB desensitization point as high as 2dBm, with 27dB narrow-band conversion gain, and 35dBc interferer rejection, witch helps minimizing the loss of orthogonality effect, introduced by the short windowing, in the analog basis expansion of the input signal. The introduced multi-block design LNA, based on highly linear voltage-voltage dynamic feedback topology, filter out the UWB interferers in group #1 and #3, while amplifying the UWB WLAN signal, and shows a better trade-off between linearity, conversion gain, and power consumption. The downconversion mixer is single-balanced, with the two quadrature pairs sharing the same input transconductor. Further research, will focusing on the implementation of the frequency-domain part of the transform-domain UWB WLAN receiver, where the receiver expands the signal over a basis set, and then operates on the bas...
This paper presents an analog design methodology, which uses the selection of the inversion coeff... more This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.
2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013
ABSTRACT In this paper, a reconfigurable successive approximation analog-to-digital converter wit... more ABSTRACT In this paper, a reconfigurable successive approximation analog-to-digital converter with selectable resolutions ranging from 7 to 10 bits is presented. The circuit is implemented in IBM CMOS 0.13 μm technology, and operates with a 0.9 V supply. The simulated effective number of bits (ENOB) ranges from 6.66 to 9.75, while the simulated power consumption during a continuous conversion ranges from 194 nW (7 bits) to 418 nW (10 bits) at a sampling rate of 50 kS/s.
2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), 2012
This work presents a curvature correction method using a subthreshold current generated by an NMO... more This work presents a curvature correction method using a subthreshold current generated by an NMOS transistor with its gate and source connected. The designed BGR, used as case study, achieves a simulated temperature coefficient of 5.9 ppm/°C, while the conventional circuit achieves only 17.5 ppm/°C — the triple of the output voltage variation in the temperature range from −40 to
2010 Second International Conference on Advances in Satellite and Space Communications, 2010
ABSTRACT This paper presents the design and analysis of a low-voltage down-conversion mixer in 0.... more ABSTRACT This paper presents the design and analysis of a low-voltage down-conversion mixer in 0.18-μm CMOS for baseband frequency-domain ultra wide band SATCOM systems analog-to-digital conversion. The folded topology allows the transconductance and Local Oscillator (LO) stages to have different bias current. Consequently, the mixer implements a two-pole low-pass filter in the switching pair stage, considering the low LO pair bias current. Furthermore, the effect of LO switching pairs width on the flicker noise mixer performance is studied, and the flicker noise, DC offset trade-off is obtained with an optimum LO transistors size value. The mixer consumes 6.8 mW from a 1.8-V supply, and achieves a voltage conversion gain (CG) of 2.8-8.2 dB, a single-sideband noise figure (NF) of 11.3-34.6 dB, a second-order intermodulation intercept point (IIP2) of 42.6- 47 dBm, and a third-order intermodualtion intercept point (IIP3) of -3.8 to -2 dBm. Concerning the port-to-port isolation issue, the average simulated LO-to-RF and LO-to-IF are -85.9 and -125.3 dB respectively.
We have developed a novel analog front-end part of a wireless brain oxymeter receiver instrument ... more We have developed a novel analog front-end part of a wireless brain oxymeter receiver instrument based on near-infrared spectroreflectometry (NIRS). The NIRS receiver makes use of dynamic threshold transistors (DTMOS) for low voltage (1–V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs are in a class AB configuration, and uses DTMOS devices for input common-mode range enhancement. Post-layout simulations under a 5 pF load, using 0.18 µm CMOS technology results are, for the OTA, an input referred noise of 134 nV/√Hz at 1 kHz, and a power consumption of 16.7 µW without any extra noise reduction technique. Also, the TIA gives 208 pA/√Hz at 1 kHz, while having a power consumption of only 10.9 µW. The proposed analog front-end circuits have been used to implement a NIRS receiver instrument with improved ultra low-light level measurements, high resolution...
In this work, a very robust quadrature time-domain CMOS front-end for transform-domain UWB WLAN r... more In this work, a very robust quadrature time-domain CMOS front-end for transform-domain UWB WLAN receiver has been presented, showing 1-dB desensitization point as high as 2dBm, with 27dB narrow-band conversion gain, and 35dBc interferer rejection, witch helps minimizing the loss of orthogonality effect, introduced by the short windowing, in the analog basis expansion of the input signal. The introduced multi-block design LNA, based on highly linear voltage-voltage dynamic feedback topology, filter out the UWB interferers in group #1 and #3, while amplifying the UWB WLAN signal, and shows a better trade-off between linearity, conversion gain, and power consumption. The downconversion mixer is single-balanced, with the two quadrature pairs sharing the same input transconductor. Further research, will focusing on the implementation of the frequency-domain part of the transform-domain UWB WLAN receiver, where the receiver expands the signal over a basis set, and then operates on the bas...
This paper presents an analog design methodology, which uses the selection of the inversion coeff... more This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.
2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013
ABSTRACT In this paper, a reconfigurable successive approximation analog-to-digital converter wit... more ABSTRACT In this paper, a reconfigurable successive approximation analog-to-digital converter with selectable resolutions ranging from 7 to 10 bits is presented. The circuit is implemented in IBM CMOS 0.13 μm technology, and operates with a 0.9 V supply. The simulated effective number of bits (ENOB) ranges from 6.66 to 9.75, while the simulated power consumption during a continuous conversion ranges from 194 nW (7 bits) to 418 nW (10 bits) at a sampling rate of 50 kS/s.
2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), 2012
This work presents a curvature correction method using a subthreshold current generated by an NMO... more This work presents a curvature correction method using a subthreshold current generated by an NMOS transistor with its gate and source connected. The designed BGR, used as case study, achieves a simulated temperature coefficient of 5.9 ppm/°C, while the conventional circuit achieves only 17.5 ppm/°C — the triple of the output voltage variation in the temperature range from −40 to
2010 Second International Conference on Advances in Satellite and Space Communications, 2010
ABSTRACT This paper presents the design and analysis of a low-voltage down-conversion mixer in 0.... more ABSTRACT This paper presents the design and analysis of a low-voltage down-conversion mixer in 0.18-μm CMOS for baseband frequency-domain ultra wide band SATCOM systems analog-to-digital conversion. The folded topology allows the transconductance and Local Oscillator (LO) stages to have different bias current. Consequently, the mixer implements a two-pole low-pass filter in the switching pair stage, considering the low LO pair bias current. Furthermore, the effect of LO switching pairs width on the flicker noise mixer performance is studied, and the flicker noise, DC offset trade-off is obtained with an optimum LO transistors size value. The mixer consumes 6.8 mW from a 1.8-V supply, and achieves a voltage conversion gain (CG) of 2.8-8.2 dB, a single-sideband noise figure (NF) of 11.3-34.6 dB, a second-order intermodulation intercept point (IIP2) of 42.6- 47 dBm, and a third-order intermodualtion intercept point (IIP3) of -3.8 to -2 dBm. Concerning the port-to-port isolation issue, the average simulated LO-to-RF and LO-to-IF are -85.9 and -125.3 dB respectively.
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Papers by C. Fayomi