We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride ma... more We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO2) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.
2015 IEEE International Electron Devices Meeting (IEDM), 2015
It is the first time that the high-k/metal gate technology was used at peripheral transistors for... more It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007
... [2] H. Rusty Harris, Siddarth Krishnan, Huang-Chun Wen, Husam Alshareef, Aarthi ... Kalpat, M... more ... [2] H. Rusty Harris, Siddarth Krishnan, Huang-Chun Wen, Husam Alshareef, Aarthi ... Kalpat, ME Ramon, L. Fonseca, ZX Jiang, JK Schaffer, RI Hedge, DH Triyoso, DC Gilmer, WJ Taylor, CC Capasso, O. Adetutu, D. Sing, J. Conner, E. Luckowski, B. W. Chan, A. Haggag, S. Backer ...
An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate el... more An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 2006
Sputter-induced artifacts can create the appearance of an interfacial reaction between Hf-based f... more Sputter-induced artifacts can create the appearance of an interfacial reaction between Hf-based films and the underlying SiO2 in sputter depth profiles. A combination of front and back side Auger electron spectroscopy depth profile analysis is used to distinguish between a native interfacial reaction at the interface between HfN and SiO2 and a potential sputtering artifact. Experimental results show that a native reaction occurs; however, the extent of the reaction may be over-represented in the front side profile due to a sputter artifact component.
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 2014
ABSTRACT As advanced silicon semiconductor devices are transitioning from planar to 3D structures... more ABSTRACT As advanced silicon semiconductor devices are transitioning from planar to 3D structures, new materials and processes are needed to control the device characteristics. Atomic layer deposition (ALD) of HfxAlyCz films using hafnium chloride and trimethylaluminum precursors was combined with postdeposition anneals and ALD liners to control the device characteristics in high-k metal-gate devices. Combinatorial process methods and technologies were employed for rapid electrical and materials characterization of various materials stacks. The effective work function in metal-oxide-semiconductor capacitor devices with the HfxAlyCz layer coupled with an ALD HfO2 dielectric was quantified to be mid-gap at similar to 4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material that allows for the tuning of device threshold voltages (V-th) for anticipated multi-V-th integrated circuit devices. (C) 2014 American Vacuum Society.
The mechanism of flatband voltage roll-off (FVRO) has been investigated with capacitors fabricate... more The mechanism of flatband voltage roll-off (FVRO) has been investigated with capacitors fabricated on terraced oxide with various thicknesses of Al2O3 film deposited by atomic layer deposition. It is found that the FVRO is mainly controlled by the thickness of the bottom interfacial layer and is independent of Al2O3 thickness. This indicates that the dipole at the SiO2/Al2O3 interface is mainly responsible for the FVRO phenomenon rather than the charges. Electrostatic analysis suggests that the disruption of the interface dipole by oxygen vacancy generated in thinner bottom interfacial layer is a potential cause of the FVRO.
The impact of thin metal nitride layers on the effective work function (EWF) of poly-Si/metal gat... more The impact of thin metal nitride layers on the effective work function (EWF) of poly-Si/metal gate stacks has been investigated. The electrode stacks studied include very thin (0.5-2.0 nm) TaN x and MoN x metal layers sandwiched between the poly-Si gate and the gate dielectric. Both n and p-type polysilicon electrodes were evaluated. The results indicate that when the metal nitride layers are as thin as 0.5 nm, they can have significant effect on the polysilicon effective work function. The observed results are explained by reactions between poly-Si and the metal nitrides leading to the formation of Ta x Si y N z in the case of TaNx inter-layers. As the metal nitride inter-layers become thicker, the work function is controlled by the metal nitride EWF. Preliminary quasi-static C-V analysis shows minimal poly depletion with the metal inter-layers. Gate leakage current and fixed charges comparable to conventional polysilicon electrodes were obtained.
We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride ma... more We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO2) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.
2015 IEEE International Electron Devices Meeting (IEDM), 2015
It is the first time that the high-k/metal gate technology was used at peripheral transistors for... more It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.
2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007
... [2] H. Rusty Harris, Siddarth Krishnan, Huang-Chun Wen, Husam Alshareef, Aarthi ... Kalpat, M... more ... [2] H. Rusty Harris, Siddarth Krishnan, Huang-Chun Wen, Husam Alshareef, Aarthi ... Kalpat, ME Ramon, L. Fonseca, ZX Jiang, JK Schaffer, RI Hedge, DH Triyoso, DC Gilmer, WJ Taylor, CC Capasso, O. Adetutu, D. Sing, J. Conner, E. Luckowski, B. W. Chan, A. Haggag, S. Backer ...
An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate el... more An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 2006
Sputter-induced artifacts can create the appearance of an interfacial reaction between Hf-based f... more Sputter-induced artifacts can create the appearance of an interfacial reaction between Hf-based films and the underlying SiO2 in sputter depth profiles. A combination of front and back side Auger electron spectroscopy depth profile analysis is used to distinguish between a native interfacial reaction at the interface between HfN and SiO2 and a potential sputtering artifact. Experimental results show that a native reaction occurs; however, the extent of the reaction may be over-represented in the front side profile due to a sputter artifact component.
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 2014
ABSTRACT As advanced silicon semiconductor devices are transitioning from planar to 3D structures... more ABSTRACT As advanced silicon semiconductor devices are transitioning from planar to 3D structures, new materials and processes are needed to control the device characteristics. Atomic layer deposition (ALD) of HfxAlyCz films using hafnium chloride and trimethylaluminum precursors was combined with postdeposition anneals and ALD liners to control the device characteristics in high-k metal-gate devices. Combinatorial process methods and technologies were employed for rapid electrical and materials characterization of various materials stacks. The effective work function in metal-oxide-semiconductor capacitor devices with the HfxAlyCz layer coupled with an ALD HfO2 dielectric was quantified to be mid-gap at similar to 4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material that allows for the tuning of device threshold voltages (V-th) for anticipated multi-V-th integrated circuit devices. (C) 2014 American Vacuum Society.
The mechanism of flatband voltage roll-off (FVRO) has been investigated with capacitors fabricate... more The mechanism of flatband voltage roll-off (FVRO) has been investigated with capacitors fabricated on terraced oxide with various thicknesses of Al2O3 film deposited by atomic layer deposition. It is found that the FVRO is mainly controlled by the thickness of the bottom interfacial layer and is independent of Al2O3 thickness. This indicates that the dipole at the SiO2/Al2O3 interface is mainly responsible for the FVRO phenomenon rather than the charges. Electrostatic analysis suggests that the disruption of the interface dipole by oxygen vacancy generated in thinner bottom interfacial layer is a potential cause of the FVRO.
The impact of thin metal nitride layers on the effective work function (EWF) of poly-Si/metal gat... more The impact of thin metal nitride layers on the effective work function (EWF) of poly-Si/metal gate stacks has been investigated. The electrode stacks studied include very thin (0.5-2.0 nm) TaN x and MoN x metal layers sandwiched between the poly-Si gate and the gate dielectric. Both n and p-type polysilicon electrodes were evaluated. The results indicate that when the metal nitride layers are as thin as 0.5 nm, they can have significant effect on the polysilicon effective work function. The observed results are explained by reactions between poly-Si and the metal nitrides leading to the formation of Ta x Si y N z in the case of TaNx inter-layers. As the metal nitride inter-layers become thicker, the work function is controlled by the metal nitride EWF. Preliminary quasi-static C-V analysis shows minimal poly depletion with the metal inter-layers. Gate leakage current and fixed charges comparable to conventional polysilicon electrodes were obtained.
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