ABSTRACT Recent research trend of passive RFID based sensors has posed stringent low power requir... more ABSTRACT Recent research trend of passive RFID based sensors has posed stringent low power requirement for energy efficient communication, which can be addressed by sub/near-Vt operation with standard CMOS process. This paper discusses new design challenges under scaled voltages and presents critical building blocks for low power protocol processing. Two supply viltages -0.45V and 0.7V are selected for powering digital and analog circuits which process EPC Gen-2 physical layer data. The design was fabricated in 180nm CMOS process and probe station measurement are reported.
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2001
This paper reports the SOI implementation of a multi-bit ▵Σ A/DC (Analog... more This paper reports the SOI implementation of a multi-bit ▵Σ A/DC (Analog to Digital Converter) without using a correction RAM (Random Access Memory). By utilizing a shift register to store the data from a quantizer in parallel and then feedback serially into a one-bit D/AC (Digital to Analog Converter), multi-bit D/AC non-linearity can be eliminated. The reduction of the drain-to-body
2008 IEEE Wireless Communications and Networking Conference, 2008
... Position Location in Forests1 Christopher L. Hutchens, Brian R. Sarbin, Alyse C. Bowers, Jaso... more ... Position Location in Forests1 Christopher L. Hutchens, Brian R. Sarbin, Alyse C. Bowers, Jason DG McKillican, Kyle K. Forrester and R. Michael Buehrer, Senior Member, IEEE T ... pp.400-404, 18-21 May 2004. [7] N. Patwari, AO Hero III, M. Perkins, NS Correal and RJ O'Dea ...
2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2013
ABSTRACT Implementing variable frequency modulation using low-cost digital signal processors intr... more ABSTRACT Implementing variable frequency modulation using low-cost digital signal processors introduces two main design issues: variability in the converter response due to the modulator delay, and a widely varying controller response due to the changing sampling period. While the first issue has been modeled several times in literature, the second has been largely ignored, and becomes an even greater issue as the frequency range is increased. As a solution, a digital compensator with adaptive gains that is normalized against frequency variations is proposed. A method for calculating the coefficients is also provided, along with a theoretical analysis of the converter frequency response. The frequency-normalized compensator is then implemented on a 180W prototype dc-dc converter, and the improvements in converter stability and system bandwidth are verified experimentally using a frequency response analyzer. For a frequency range of 25–75kHz, bandwidth improvements of up to 300% are shown for the prototype system.
Region 5 Conference: Annual Technical and Leadership Workshop, 2004, 2004
EKV model parameters are extracted from the partially depleted (PD) SOI MOSFET fabricated in 0.5 ... more EKV model parameters are extracted from the partially depleted (PD) SOI MOSFET fabricated in 0.5 μm Peregrine process. The simulated I-V curves match the measured data very well.
2012 IEEE Energy Conversion Congress and Exposition (ECCE), 2012
ABSTRACT This paper presents an analysis of losses that occur during dead time in an active-clamp... more ABSTRACT This paper presents an analysis of losses that occur during dead time in an active-clamp flyback converter utilizing Gallium Nitride based MOSFETs. This analysis is used to optimize the length of the dead-time period in order to minimize losses in the switching devices. When compared to silicon-based MOSFETs, GaN-based MOSFETs have lower switching losses and much higher reverse conduction losses, so it is not desirable to design for zero-voltage switching (ZVS) over a wide load range. The analysis presented in this paper finds an optimal trade-off between partial ZVS and reverse conduction losses, minimizing overall device switching losses and therefore increasing converter efficiency over the desired load range. A 15-W, four-output active-clamp flyback converter utilizing GaN devices at 1 MHz is designed and implemented using the recommended optimization. The experimental results confirm this analysis and result in a minimization of switching losses and an increase in converter efficiency.
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
ABSTRACT This paper presents the design of a low power digital baseband core with a custom-tailor... more ABSTRACT This paper presents the design of a low power digital baseband core with a custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) system on a chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of multiple sensors, is designed to control the operation and the interface with the whole MNI SoC based on received downlink commands and store/dump targeted neural data uplink in an energy efficient way. Robust low power cell library and on-chip SRAM memory are specially designed to achieve robust low-voltage operation with targeted timing constraints. The average measured power is 2μW at 1.28MHz system clock under 450mV power supply and a communication data rate of 640Kbps.
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012
ABSTRACT An 8 bit, 1.5 b/stage fully differential (FD) multiplying digital to analog converter (M... more ABSTRACT An 8 bit, 1.5 b/stage fully differential (FD) multiplying digital to analog converter (MDAC) pipeline ADC for use in a smart RFID is presented in this paper. The FD Operational Transconductance Amplifier (OTA) in the MDAC utilizes a novel common mode (CM) amplifier, which is inherently stable demonstrating reduced common mode offset and improved compensation tracking across process. Furthermore, a simple offset cancellation technique robust to device leakage is introduced to correct error due to leakage induced input offset voltage drift. Monte Carlo simulation results show that for the input voltage range of ±400mV, ADC can achieve 8 ENOB with sampling frequency at 16 kHz. Total ADC power consumption is 5.1uA with 0.7V power supply. The ADC was submitted for fabrication in 180nm CMOS with results forth coming.
2008 51st Midwest Symposium on Circuits and Systems, 2008
ABSTRACT This paper presents a 2.4 GHz RF front end for use in a wireless powered micro neural in... more ABSTRACT This paper presents a 2.4 GHz RF front end for use in a wireless powered micro neural interface systems. The front end consists of a matching network and a two stage rectifier. A programmable current source is included for circuit validation. There is a great and growing need for wirelessly powering biological implants. Specifically, we are addressing a need for neural sensors and stimulators were total power dissipation must be less than 1 mW for safety reasons. Subthreshold CMOS analog circuits operate successfully over a large range of supply voltages. A wide range of output voltages from -250 mV up to 2.4V are observed when varying the load current at a fixed input power and vice versa. The total chip area including bond pads is 0.730 mm2.The designs were fabricated using peregrine 0.5 micron silicon on sapphire process.
We present techniques for designing high temperature analog circuits using Peregrine Semiconducto... more We present techniques for designing high temperature analog circuits using Peregrine Semiconductor's Silicon-on-Sapphire (SOS) process, a process originally designed for digital and limited RF applications. Peregrine's process is nominally a fully depleted SOS thin film process, but it tends to exhibit a troublesome kink effect when used for analog applications. For analog applications, we have developed high temperature SPICE BSIM3SOI
The design of a switched-mode power supply (SMPS) employing V2 control architecture for operation... more The design of a switched-mode power supply (SMPS) employing V2 control architecture for operation in excess of 225°C has been explored. The objective of the study is to prove the feasibility of a high-temperature SMPS and to determine the design metrics on the individual components to insure system stability over 25°C to 225°C. The study details the working of the
The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and... more The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and signal processing applications. This high temperature version of the 68HC11 enables new high temperature designs and additionally allows 68HC11-based well logging tools and MWD tools to be upgraded for high temperature operation in deep gas reservoirs. In this project, funded by the U. S. Department
2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010
... Smith, and Tim Hegarty National Semiconductor Corporation Santa Clara, CA, USA Jianhui.Zhang@... more ... Smith, and Tim Hegarty National Semiconductor Corporation Santa Clara, CA, USA Jianhui.Zhang@nsc.com, Gianpaolo.Lisi@nsc.com, Ali.Djabbari@nsc ... can be calculated based on the design criterion that the maximum magnitude of the peak-to-peak current ripple is less ...
2013 IEEE Antennas and Propagation Society International Symposium (APSURSI), 2013
ABSTRACT An antenna has been designed for use with a UHF band (902–928 MHz) RFID tag for implanta... more ABSTRACT An antenna has been designed for use with a UHF band (902–928 MHz) RFID tag for implantation in live human brain tissue as the front end for a smart RFID. The COMSOL computational electromagnetic package was used for the design process. The COMSOL model was validated against the measurement of several test antennas when radiating into a bulk homogenous medium simulating human tissue. The proposed antenna is a 22 mm by 3.5 mm planar folded dipole consisting of a thin gold conductor (1 µm thick) placed on a dielectric substrate and coated with acrylic, giving a bio-compatible structure. The folded dipole dimensions are chosen to give an inductive input impedance that provides a good match to the capacitive load of the RFID tag when operating within brain tissue to maintain near optimal harvest efficiency.
Region 5 Conference: Annual Technical and Leadership Workshop, 2004, 2004
... Jianning Wang, Jason Rowland**, Xunyu Zhu*, Chris Hutchens, Yumin Zhang* * Oklahoma State U... more ... Jianning Wang, Jason Rowland**, Xunyu Zhu*, Chris Hutchens, Yumin Zhang* * Oklahoma State University, Stillwater, OK 74078 ... a). However, including these parasitic circuit elements makes the extraction of the important intrinsic inductor parameters very tricky and inaccurate ...
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004., 2004
Seven-stage and twenty-one-stage voltage controlled inverter-chain ring oscillators are fabricate... more Seven-stage and twenty-one-stage voltage controlled inverter-chain ring oscillators are fabricated in SOI 0.5 μm technology. It is found that the oscillation is very robust to the variation of power supply voltage, and there is no significant change of timing jitter. When the body voltages of the MOSFETs are swept, the oscillation frequency has a linear dependence.
This paper presents an RF model of an accumulation-mode MOS varactor with a high capacitance tuni... more This paper presents an RF model of an accumulation-mode MOS varactor with a high capacitance tuning range in a multi-finger layout. This model is based on the physical parameters of the device, and it can describe the voltage dependent capacitance, as well as the parasitic circuit elements. It employs a single topology with lumped elements derived from the device, so
Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2014
A low power, low noise implantable neural recording interface for use in a Radio-Frequency Identi... more A low power, low noise implantable neural recording interface for use in a Radio-Frequency Identification (RFID) is presented in this paper. A two stage neural amplifier and 8 bit Pipelined Analog to Digital Converter (ADC) are integrated in this system. The optimized number of amplifier stages demonstrates the minimum power and area consumption; The ADC utilizes a novel offset cancellation technique robust to device leakage to reduce the input offset voltage. The neural amplifier and ADC both utilize 700mV power supply. The midband gain of neural amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7μVrms and 1.90 respectively. The ADC achieves 8 bit accuracy at 16Ksps with an input voltage of ±400mV. Combined simulation and measurement results demonstrate the neural recording interface's suitability for in situ neutral activity recording.
ABSTRACT Recent research trend of passive RFID based sensors has posed stringent low power requir... more ABSTRACT Recent research trend of passive RFID based sensors has posed stringent low power requirement for energy efficient communication, which can be addressed by sub/near-Vt operation with standard CMOS process. This paper discusses new design challenges under scaled voltages and presents critical building blocks for low power protocol processing. Two supply viltages -0.45V and 0.7V are selected for powering digital and analog circuits which process EPC Gen-2 physical layer data. The design was fabricated in 180nm CMOS process and probe station measurement are reported.
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2001
This paper reports the SOI implementation of a multi-bit ▵Σ A/DC (Analog... more This paper reports the SOI implementation of a multi-bit ▵Σ A/DC (Analog to Digital Converter) without using a correction RAM (Random Access Memory). By utilizing a shift register to store the data from a quantizer in parallel and then feedback serially into a one-bit D/AC (Digital to Analog Converter), multi-bit D/AC non-linearity can be eliminated. The reduction of the drain-to-body
2008 IEEE Wireless Communications and Networking Conference, 2008
... Position Location in Forests1 Christopher L. Hutchens, Brian R. Sarbin, Alyse C. Bowers, Jaso... more ... Position Location in Forests1 Christopher L. Hutchens, Brian R. Sarbin, Alyse C. Bowers, Jason DG McKillican, Kyle K. Forrester and R. Michael Buehrer, Senior Member, IEEE T ... pp.400-404, 18-21 May 2004. [7] N. Patwari, AO Hero III, M. Perkins, NS Correal and RJ O'Dea ...
2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2013
ABSTRACT Implementing variable frequency modulation using low-cost digital signal processors intr... more ABSTRACT Implementing variable frequency modulation using low-cost digital signal processors introduces two main design issues: variability in the converter response due to the modulator delay, and a widely varying controller response due to the changing sampling period. While the first issue has been modeled several times in literature, the second has been largely ignored, and becomes an even greater issue as the frequency range is increased. As a solution, a digital compensator with adaptive gains that is normalized against frequency variations is proposed. A method for calculating the coefficients is also provided, along with a theoretical analysis of the converter frequency response. The frequency-normalized compensator is then implemented on a 180W prototype dc-dc converter, and the improvements in converter stability and system bandwidth are verified experimentally using a frequency response analyzer. For a frequency range of 25–75kHz, bandwidth improvements of up to 300% are shown for the prototype system.
Region 5 Conference: Annual Technical and Leadership Workshop, 2004, 2004
EKV model parameters are extracted from the partially depleted (PD) SOI MOSFET fabricated in 0.5 ... more EKV model parameters are extracted from the partially depleted (PD) SOI MOSFET fabricated in 0.5 μm Peregrine process. The simulated I-V curves match the measured data very well.
2012 IEEE Energy Conversion Congress and Exposition (ECCE), 2012
ABSTRACT This paper presents an analysis of losses that occur during dead time in an active-clamp... more ABSTRACT This paper presents an analysis of losses that occur during dead time in an active-clamp flyback converter utilizing Gallium Nitride based MOSFETs. This analysis is used to optimize the length of the dead-time period in order to minimize losses in the switching devices. When compared to silicon-based MOSFETs, GaN-based MOSFETs have lower switching losses and much higher reverse conduction losses, so it is not desirable to design for zero-voltage switching (ZVS) over a wide load range. The analysis presented in this paper finds an optimal trade-off between partial ZVS and reverse conduction losses, minimizing overall device switching losses and therefore increasing converter efficiency over the desired load range. A 15-W, four-output active-clamp flyback converter utilizing GaN devices at 1 MHz is designed and implemented using the recommended optimization. The experimental results confirm this analysis and result in a minimization of switching losses and an increase in converter efficiency.
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
ABSTRACT This paper presents the design of a low power digital baseband core with a custom-tailor... more ABSTRACT This paper presents the design of a low power digital baseband core with a custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) system on a chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of multiple sensors, is designed to control the operation and the interface with the whole MNI SoC based on received downlink commands and store/dump targeted neural data uplink in an energy efficient way. Robust low power cell library and on-chip SRAM memory are specially designed to achieve robust low-voltage operation with targeted timing constraints. The average measured power is 2μW at 1.28MHz system clock under 450mV power supply and a communication data rate of 640Kbps.
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012
ABSTRACT An 8 bit, 1.5 b/stage fully differential (FD) multiplying digital to analog converter (M... more ABSTRACT An 8 bit, 1.5 b/stage fully differential (FD) multiplying digital to analog converter (MDAC) pipeline ADC for use in a smart RFID is presented in this paper. The FD Operational Transconductance Amplifier (OTA) in the MDAC utilizes a novel common mode (CM) amplifier, which is inherently stable demonstrating reduced common mode offset and improved compensation tracking across process. Furthermore, a simple offset cancellation technique robust to device leakage is introduced to correct error due to leakage induced input offset voltage drift. Monte Carlo simulation results show that for the input voltage range of ±400mV, ADC can achieve 8 ENOB with sampling frequency at 16 kHz. Total ADC power consumption is 5.1uA with 0.7V power supply. The ADC was submitted for fabrication in 180nm CMOS with results forth coming.
2008 51st Midwest Symposium on Circuits and Systems, 2008
ABSTRACT This paper presents a 2.4 GHz RF front end for use in a wireless powered micro neural in... more ABSTRACT This paper presents a 2.4 GHz RF front end for use in a wireless powered micro neural interface systems. The front end consists of a matching network and a two stage rectifier. A programmable current source is included for circuit validation. There is a great and growing need for wirelessly powering biological implants. Specifically, we are addressing a need for neural sensors and stimulators were total power dissipation must be less than 1 mW for safety reasons. Subthreshold CMOS analog circuits operate successfully over a large range of supply voltages. A wide range of output voltages from -250 mV up to 2.4V are observed when varying the load current at a fixed input power and vice versa. The total chip area including bond pads is 0.730 mm2.The designs were fabricated using peregrine 0.5 micron silicon on sapphire process.
We present techniques for designing high temperature analog circuits using Peregrine Semiconducto... more We present techniques for designing high temperature analog circuits using Peregrine Semiconductor's Silicon-on-Sapphire (SOS) process, a process originally designed for digital and limited RF applications. Peregrine's process is nominally a fully depleted SOS thin film process, but it tends to exhibit a troublesome kink effect when used for analog applications. For analog applications, we have developed high temperature SPICE BSIM3SOI
The design of a switched-mode power supply (SMPS) employing V2 control architecture for operation... more The design of a switched-mode power supply (SMPS) employing V2 control architecture for operation in excess of 225°C has been explored. The objective of the study is to prove the feasibility of a high-temperature SMPS and to determine the design metrics on the individual components to insure system stability over 25°C to 225°C. The study details the working of the
The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and... more The 68HC11 microprocessor is widely used in well logging tools for control, data acquisition, and signal processing applications. This high temperature version of the 68HC11 enables new high temperature designs and additionally allows 68HC11-based well logging tools and MWD tools to be upgraded for high temperature operation in deep gas reservoirs. In this project, funded by the U. S. Department
2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010
... Smith, and Tim Hegarty National Semiconductor Corporation Santa Clara, CA, USA Jianhui.Zhang@... more ... Smith, and Tim Hegarty National Semiconductor Corporation Santa Clara, CA, USA Jianhui.Zhang@nsc.com, Gianpaolo.Lisi@nsc.com, Ali.Djabbari@nsc ... can be calculated based on the design criterion that the maximum magnitude of the peak-to-peak current ripple is less ...
2013 IEEE Antennas and Propagation Society International Symposium (APSURSI), 2013
ABSTRACT An antenna has been designed for use with a UHF band (902–928 MHz) RFID tag for implanta... more ABSTRACT An antenna has been designed for use with a UHF band (902–928 MHz) RFID tag for implantation in live human brain tissue as the front end for a smart RFID. The COMSOL computational electromagnetic package was used for the design process. The COMSOL model was validated against the measurement of several test antennas when radiating into a bulk homogenous medium simulating human tissue. The proposed antenna is a 22 mm by 3.5 mm planar folded dipole consisting of a thin gold conductor (1 µm thick) placed on a dielectric substrate and coated with acrylic, giving a bio-compatible structure. The folded dipole dimensions are chosen to give an inductive input impedance that provides a good match to the capacitive load of the RFID tag when operating within brain tissue to maintain near optimal harvest efficiency.
Region 5 Conference: Annual Technical and Leadership Workshop, 2004, 2004
... Jianning Wang, Jason Rowland**, Xunyu Zhu*, Chris Hutchens, Yumin Zhang* * Oklahoma State U... more ... Jianning Wang, Jason Rowland**, Xunyu Zhu*, Chris Hutchens, Yumin Zhang* * Oklahoma State University, Stillwater, OK 74078 ... a). However, including these parasitic circuit elements makes the extraction of the important intrinsic inductor parameters very tricky and inaccurate ...
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004., 2004
Seven-stage and twenty-one-stage voltage controlled inverter-chain ring oscillators are fabricate... more Seven-stage and twenty-one-stage voltage controlled inverter-chain ring oscillators are fabricated in SOI 0.5 μm technology. It is found that the oscillation is very robust to the variation of power supply voltage, and there is no significant change of timing jitter. When the body voltages of the MOSFETs are swept, the oscillation frequency has a linear dependence.
This paper presents an RF model of an accumulation-mode MOS varactor with a high capacitance tuni... more This paper presents an RF model of an accumulation-mode MOS varactor with a high capacitance tuning range in a multi-finger layout. This model is based on the physical parameters of the device, and it can describe the voltage dependent capacitance, as well as the parasitic circuit elements. It employs a single topology with lumped elements derived from the device, so
Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2014
A low power, low noise implantable neural recording interface for use in a Radio-Frequency Identi... more A low power, low noise implantable neural recording interface for use in a Radio-Frequency Identification (RFID) is presented in this paper. A two stage neural amplifier and 8 bit Pipelined Analog to Digital Converter (ADC) are integrated in this system. The optimized number of amplifier stages demonstrates the minimum power and area consumption; The ADC utilizes a novel offset cancellation technique robust to device leakage to reduce the input offset voltage. The neural amplifier and ADC both utilize 700mV power supply. The midband gain of neural amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7μVrms and 1.90 respectively. The ADC achieves 8 bit accuracy at 16Ksps with an input voltage of ±400mV. Combined simulation and measurement results demonstrate the neural recording interface's suitability for in situ neutral activity recording.
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Papers by Chris Hutchens