ABSTRACT Issues with typical low-cost, low-power sensor nodes in System-on-Chip designs include c... more ABSTRACT Issues with typical low-cost, low-power sensor nodes in System-on-Chip designs include component integration, energy efficiency and reusability. These are solved by implementing a standard communication protocol like the Advanced Microcontroller Bus Architecture (AMBA) that allows low-power designs. An AMBA system prototype is designed, implemented, and characterized on an FPGA platform, with ARM9TDM as the processor, SRAM as memory device, and Ethernet, LCD, UART, and PS/2 as peripherals. With this base platform, other sensor node components like the transceiver, ADC and sensors can be easily integrated to obtain a completely functional node for sensor networks.
Stem cell replacement holds the potential for sensorineural hearing loss (SNHL) treatment. Howeve... more Stem cell replacement holds the potential for sensorineural hearing loss (SNHL) treatment. However, its translation into clinical practice requires strategies for improving stem cell survival following intracochlear transplantation. Considering recent findings showing that the inner ear contains a resident population of immune cells, we hypothesized that immune evasion would improve the survival and residence time of transplanted stem cells in the cochlea, potentially leading to better outcomes. To test this, we leveraged genetic engineering techniques to develop hypoimmunogenic human-induced pluripotent stem cells (hi-iPSC), which lack human leukocyte antigen expression. We found that gene editing does not affect the biological properties of hi-iPSCs, including their capacity to differentiate into otic neural progenitors (ONPs). Compared to wild-type ONPs, more hypoimmunogenic ONPs (derived from hi-iPSCs) were found in the inner ear of immunocompetent mice ten days following cochle...
2020 IEEE 12th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management (HNICEM), 2020
Sensitivity issues of the internal design rule check (DRC) capability of an electronic design aut... more Sensitivity issues of the internal design rule check (DRC) capability of an electronic design automation tool are highlighted when the design technology used is not properly configured. However, the integration of computer vision and computational intelligence in the field of constraint engineering and integrated circuit layout has high tendency to resolve this ambiguity. In this study, vision-based architecture is integrated with deep transfer learning network to classify NOT, NAND (no fold and two-finger), and NOR logic gates with 1 $\mu \mathrm{m}$ physical gate polysilicon and 0.5 ${\mu} \mathrm{m}$ gate length using 90 nm CMOS technology. Inverter designs with contact (CO) error is generated using missing CO, metal 1 in place and not fully placed, and off positioned CO via an incorporated Python-triggered tool command language (TCL) program in the Synopsys platform. EfficientNetB7 perfectly classified NOT and NAND gates, and subcategorized NOT contact error designs. Overall, the developed seamless approach in classifying gate-level integrated circuit design and predicting contact errors using EfficientNetB7 is easy to replicate and can enhance layout assessment.
2020 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC), 2020
In response to the emerging challenges of providing intelligent dynamic integrated circuit (IC) l... more In response to the emerging challenges of providing intelligent dynamic integrated circuit (IC) layout checking, computer vision in IC design and constraint engineering highlights the opportunities of computational intelligence solutions. In this study, vision-based system architecture is integrated with deep transfer learning models to classify metal oxide semiconductor (MOS) transistor cell-level layout error using one-vs-rest (OvR) multilabel classification. Two layout errors, namely missing contact layer and excess structure around the gate, are generated using the developed tool command language (TCL) script that is executed on Synopsys platform. Missing contact layer error is furtherly subcategorized to metal 1 in place and not fully placed, off positioned contact and its combination. Excess structure around the transistor gate is characterized by excess p-type implant (PIMP) and n-type implant (NIMP) with misaligned diffusion (DIFF) and polysilicon (PO) layers. Feature extraction for MOS-level error classification explored on using MobileNetV2 and EfficientNet variants. It was found that EfficientNetB7 best MobileNetV2 and other variants of EfficientNet in predicting IC layout errors based on nine error subcategories. Hamming loss was found to decrease and inference time to increase as the input image size is increased. The deep transfer network EfficientNetB7 has accuracy of 96.889 %, precision of 88.778 %, recall of 97.444 % and F1score of 91.667 in predicting transistor-level layout errors. Overall, the developed approach in predicting MOS transistor cell-level layout error using integrated computer vision and deep learning proved to be accurate and easy to be replicated for further enhancement to provide advanced layout evaluation.
Stem cell-replacement therapies have been proposed as a potential tool to treat sensorineural hea... more Stem cell-replacement therapies have been proposed as a potential tool to treat sensorineural hearing loss by aiding the regeneration of spiral ganglion neurons in the inner ear. However, transplantation procedures have yet to be explored thoroughly to ensure proper cell differentiation and optimal transplant procedures. We hypothesized that the aggregation of human embryonic stem cell-derived otic neuronal progenitor cells into a multicellular form would improve their function and their survival in vivo post-transplantation. We generated human embryonic stem cell-derived otic neuronal progenitor spheroids-an aggregate form conducive to differentiation, transplantation, and prolonged cell survival-to optimize conditions for their transplantation. Our findings indicate that these cell spheroids maintain the molecular and functional characteristics similar to those of otic neuronal progenitor cells, which are upstream in the spiral ganglion neuron lineage. Moreover, our phenotypical, electrophysiological, and mechanical data suggest an optimal spheroid transplantation point after seven days of in vitro three-dimensional culture. We have also developed a feasible transplantation protocol for these spheroids using a micropipette aided by a digital micro-injection system. In summary, the present work demonstrates that the transplantation of otic neuronal progenitor cells in spheroid form into the inner ear via micropipette seven days after seeding for three-dimensional spheroid culture is an expedient and viable method for stem cell-replacement therapies in the inner ear.
2015 International Conference on Humanoid, Nanotechnology, Information Technology,Communication and Control, Environment and Management (HNICEM), 2015
Existing replenishment system in vending machines can only periodically review the inventories. M... more Existing replenishment system in vending machines can only periodically review the inventories. Moreover, current vending machines are not capable of determining if the supplies are subject to replenishment or not. This result to an inefficient replenishment policy and there will be frequent stock-out among the products. This research aims to develop a smart vending machine that provides inventory and logistic support for the operator. The intelligent system is controlled by a fuzzy system which outputs the crisp values which will be represented by the Resupply Alert Index (RAI), a decimal number representation that ranges from 0-3 with 0 as `urgent' status and 3 as `ok' status; this gives the operator which of the supplies needs replenishment. By implementing this study, stock-out among the vending machines will be prevented and an efficient replenishment system will be implemented. The application used for the implementation of this system is a paper dispensing machine that covers the demand in the Faculty of Engineering of the University Of Santo Tomas and compared with other virtual simulations. Through the simulations, it was established that the RAI can give the supplier the information of which vending machine and which of its products has the highest replenishment urgency.
ABSTRACT A 1V unregulated DC voltage from the rectifier of an energy harvesting node is converted... more ABSTRACT A 1V unregulated DC voltage from the rectifier of an energy harvesting node is converted down to 650mV regulated DC voltage with 10mV ripple (maximum frequency is 100MHz) by the switched-capacitor converter (SCC) that can supply up to 2.5mA current. For more supply sensitive loads such as RF blocks, a low dropout (LDO) voltage regulator steps down the SCC's output to 500mV regulated DC voltage with at most 1.4% ripple. The LDO can supply a maximum load current of 1mA with 0.98% load regulation. Simulation results in 90nm CMOS show that the SCC has a maximum efficiency of 71% while the LDO has a maximum efficiency of 70.8% at maximum load current.
2013 IEEE International Conference on Microelectronic Systems Education (MSE), 2013
ABSTRACT The Eye-C program was instituted to enable a collaborative IC design effort among differ... more ABSTRACT The Eye-C program was instituted to enable a collaborative IC design effort among different universities in the Philippines. This paper presents the impact of the program on the member universities' curriculum during and after its implementation. A post-implementation review by member universities is then presented to further highlight the Eye-C program as the first of a series of steps to enhance the potential of microelectronics in the Philippines.
TENCON 2010 - 2010 IEEE Region 10 Conference, 2010
Page 1. System-level Simulation and Analysis of a WiMAX Direct-conversion Receiver in 90nm CMOS L... more Page 1. System-level Simulation and Analysis of a WiMAX Direct-conversion Receiver in 90nm CMOS Lendl Israel M. Alunan, Maria Theresa G. de Leon and Christian Raymund K. Roque Electrical and Electronics Engineering ...
ABSTRACT In this study, two parameter enhancement techniques, Transformer-based power combining a... more ABSTRACT In this study, two parameter enhancement techniques, Transformer-based power combining and Diode linearization, which can improve the performance of a power amplifier, are implemented on a Class AB PA and then combined to determine their effectiveness. Using a 1.2-V 90nm CMOS process, a test chip containing the power combining network is fabricated and tested. The obtained results show that the power combining technique increases POUT by 13dB in exchange of 2X die area increase. The diode linearizer improves 1-dB input compression point by 1.3dB, IM3 up to 5dB and APC first offset frequency WiMAX specification by 10dB. These are all attained in exchange of a 1.1dB insertion loss.
TENCON 2010 - 2010 IEEE Region 10 Conference, 2010
In RF energy harvesting scheme, the acquired voltage level is too low to be considered as a suppl... more In RF energy harvesting scheme, the acquired voltage level is too low to be considered as a supply voltage of applications such as microsensors. Therefore, there is a need to increase this value, and passive voltage multiplier is a solution to this requirement. In this project, two passive voltage multipliers, namely, Modified Dickson (MDVM) and Mandal-Sarpeshkar (MSVM) voltage multipliers are designed and implemented. From a mere input power of 10 μW to 60 μW at 13.56 MHz, the voltage multipliers effectively increased the output voltage to 905 mV to 2.128 V and 1.114 V to 3.609 V for MDVM and MSVM, respectively, given a supply voltage of 1 V and a capacitive load of 30 pF. All designs are implemented using 90 nm CMOS process.
TENCON 2011 - 2011 IEEE Region 10 Conference, 2011
This project is an implementation of a runtime memory simulator with a compiler-assembler for the... more This project is an implementation of a runtime memory simulator with a compiler-assembler for the ARM7 microprocessor with multi-core and floating point operation capability. Compiler support is extended to floating point computations. Also, the integrated development environment (IDE) features selective optimization for compilation. The target outputs are the assembly codes following the instruction set architecture (ISA) of the ARM7 and
ABSTRACT Issues with typical low-cost, low-power sensor nodes in System-on-Chip designs include c... more ABSTRACT Issues with typical low-cost, low-power sensor nodes in System-on-Chip designs include component integration, energy efficiency and reusability. These are solved by implementing a standard communication protocol like the Advanced Microcontroller Bus Architecture (AMBA) that allows low-power designs. An AMBA system prototype is designed, implemented, and characterized on an FPGA platform, with ARM9TDM as the processor, SRAM as memory device, and Ethernet, LCD, UART, and PS/2 as peripherals. With this base platform, other sensor node components like the transceiver, ADC and sensors can be easily integrated to obtain a completely functional node for sensor networks.
Stem cell replacement holds the potential for sensorineural hearing loss (SNHL) treatment. Howeve... more Stem cell replacement holds the potential for sensorineural hearing loss (SNHL) treatment. However, its translation into clinical practice requires strategies for improving stem cell survival following intracochlear transplantation. Considering recent findings showing that the inner ear contains a resident population of immune cells, we hypothesized that immune evasion would improve the survival and residence time of transplanted stem cells in the cochlea, potentially leading to better outcomes. To test this, we leveraged genetic engineering techniques to develop hypoimmunogenic human-induced pluripotent stem cells (hi-iPSC), which lack human leukocyte antigen expression. We found that gene editing does not affect the biological properties of hi-iPSCs, including their capacity to differentiate into otic neural progenitors (ONPs). Compared to wild-type ONPs, more hypoimmunogenic ONPs (derived from hi-iPSCs) were found in the inner ear of immunocompetent mice ten days following cochle...
2020 IEEE 12th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management (HNICEM), 2020
Sensitivity issues of the internal design rule check (DRC) capability of an electronic design aut... more Sensitivity issues of the internal design rule check (DRC) capability of an electronic design automation tool are highlighted when the design technology used is not properly configured. However, the integration of computer vision and computational intelligence in the field of constraint engineering and integrated circuit layout has high tendency to resolve this ambiguity. In this study, vision-based architecture is integrated with deep transfer learning network to classify NOT, NAND (no fold and two-finger), and NOR logic gates with 1 $\mu \mathrm{m}$ physical gate polysilicon and 0.5 ${\mu} \mathrm{m}$ gate length using 90 nm CMOS technology. Inverter designs with contact (CO) error is generated using missing CO, metal 1 in place and not fully placed, and off positioned CO via an incorporated Python-triggered tool command language (TCL) program in the Synopsys platform. EfficientNetB7 perfectly classified NOT and NAND gates, and subcategorized NOT contact error designs. Overall, the developed seamless approach in classifying gate-level integrated circuit design and predicting contact errors using EfficientNetB7 is easy to replicate and can enhance layout assessment.
2020 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC), 2020
In response to the emerging challenges of providing intelligent dynamic integrated circuit (IC) l... more In response to the emerging challenges of providing intelligent dynamic integrated circuit (IC) layout checking, computer vision in IC design and constraint engineering highlights the opportunities of computational intelligence solutions. In this study, vision-based system architecture is integrated with deep transfer learning models to classify metal oxide semiconductor (MOS) transistor cell-level layout error using one-vs-rest (OvR) multilabel classification. Two layout errors, namely missing contact layer and excess structure around the gate, are generated using the developed tool command language (TCL) script that is executed on Synopsys platform. Missing contact layer error is furtherly subcategorized to metal 1 in place and not fully placed, off positioned contact and its combination. Excess structure around the transistor gate is characterized by excess p-type implant (PIMP) and n-type implant (NIMP) with misaligned diffusion (DIFF) and polysilicon (PO) layers. Feature extraction for MOS-level error classification explored on using MobileNetV2 and EfficientNet variants. It was found that EfficientNetB7 best MobileNetV2 and other variants of EfficientNet in predicting IC layout errors based on nine error subcategories. Hamming loss was found to decrease and inference time to increase as the input image size is increased. The deep transfer network EfficientNetB7 has accuracy of 96.889 %, precision of 88.778 %, recall of 97.444 % and F1score of 91.667 in predicting transistor-level layout errors. Overall, the developed approach in predicting MOS transistor cell-level layout error using integrated computer vision and deep learning proved to be accurate and easy to be replicated for further enhancement to provide advanced layout evaluation.
Stem cell-replacement therapies have been proposed as a potential tool to treat sensorineural hea... more Stem cell-replacement therapies have been proposed as a potential tool to treat sensorineural hearing loss by aiding the regeneration of spiral ganglion neurons in the inner ear. However, transplantation procedures have yet to be explored thoroughly to ensure proper cell differentiation and optimal transplant procedures. We hypothesized that the aggregation of human embryonic stem cell-derived otic neuronal progenitor cells into a multicellular form would improve their function and their survival in vivo post-transplantation. We generated human embryonic stem cell-derived otic neuronal progenitor spheroids-an aggregate form conducive to differentiation, transplantation, and prolonged cell survival-to optimize conditions for their transplantation. Our findings indicate that these cell spheroids maintain the molecular and functional characteristics similar to those of otic neuronal progenitor cells, which are upstream in the spiral ganglion neuron lineage. Moreover, our phenotypical, electrophysiological, and mechanical data suggest an optimal spheroid transplantation point after seven days of in vitro three-dimensional culture. We have also developed a feasible transplantation protocol for these spheroids using a micropipette aided by a digital micro-injection system. In summary, the present work demonstrates that the transplantation of otic neuronal progenitor cells in spheroid form into the inner ear via micropipette seven days after seeding for three-dimensional spheroid culture is an expedient and viable method for stem cell-replacement therapies in the inner ear.
2015 International Conference on Humanoid, Nanotechnology, Information Technology,Communication and Control, Environment and Management (HNICEM), 2015
Existing replenishment system in vending machines can only periodically review the inventories. M... more Existing replenishment system in vending machines can only periodically review the inventories. Moreover, current vending machines are not capable of determining if the supplies are subject to replenishment or not. This result to an inefficient replenishment policy and there will be frequent stock-out among the products. This research aims to develop a smart vending machine that provides inventory and logistic support for the operator. The intelligent system is controlled by a fuzzy system which outputs the crisp values which will be represented by the Resupply Alert Index (RAI), a decimal number representation that ranges from 0-3 with 0 as `urgent' status and 3 as `ok' status; this gives the operator which of the supplies needs replenishment. By implementing this study, stock-out among the vending machines will be prevented and an efficient replenishment system will be implemented. The application used for the implementation of this system is a paper dispensing machine that covers the demand in the Faculty of Engineering of the University Of Santo Tomas and compared with other virtual simulations. Through the simulations, it was established that the RAI can give the supplier the information of which vending machine and which of its products has the highest replenishment urgency.
ABSTRACT A 1V unregulated DC voltage from the rectifier of an energy harvesting node is converted... more ABSTRACT A 1V unregulated DC voltage from the rectifier of an energy harvesting node is converted down to 650mV regulated DC voltage with 10mV ripple (maximum frequency is 100MHz) by the switched-capacitor converter (SCC) that can supply up to 2.5mA current. For more supply sensitive loads such as RF blocks, a low dropout (LDO) voltage regulator steps down the SCC's output to 500mV regulated DC voltage with at most 1.4% ripple. The LDO can supply a maximum load current of 1mA with 0.98% load regulation. Simulation results in 90nm CMOS show that the SCC has a maximum efficiency of 71% while the LDO has a maximum efficiency of 70.8% at maximum load current.
2013 IEEE International Conference on Microelectronic Systems Education (MSE), 2013
ABSTRACT The Eye-C program was instituted to enable a collaborative IC design effort among differ... more ABSTRACT The Eye-C program was instituted to enable a collaborative IC design effort among different universities in the Philippines. This paper presents the impact of the program on the member universities' curriculum during and after its implementation. A post-implementation review by member universities is then presented to further highlight the Eye-C program as the first of a series of steps to enhance the potential of microelectronics in the Philippines.
TENCON 2010 - 2010 IEEE Region 10 Conference, 2010
Page 1. System-level Simulation and Analysis of a WiMAX Direct-conversion Receiver in 90nm CMOS L... more Page 1. System-level Simulation and Analysis of a WiMAX Direct-conversion Receiver in 90nm CMOS Lendl Israel M. Alunan, Maria Theresa G. de Leon and Christian Raymund K. Roque Electrical and Electronics Engineering ...
ABSTRACT In this study, two parameter enhancement techniques, Transformer-based power combining a... more ABSTRACT In this study, two parameter enhancement techniques, Transformer-based power combining and Diode linearization, which can improve the performance of a power amplifier, are implemented on a Class AB PA and then combined to determine their effectiveness. Using a 1.2-V 90nm CMOS process, a test chip containing the power combining network is fabricated and tested. The obtained results show that the power combining technique increases POUT by 13dB in exchange of 2X die area increase. The diode linearizer improves 1-dB input compression point by 1.3dB, IM3 up to 5dB and APC first offset frequency WiMAX specification by 10dB. These are all attained in exchange of a 1.1dB insertion loss.
TENCON 2010 - 2010 IEEE Region 10 Conference, 2010
In RF energy harvesting scheme, the acquired voltage level is too low to be considered as a suppl... more In RF energy harvesting scheme, the acquired voltage level is too low to be considered as a supply voltage of applications such as microsensors. Therefore, there is a need to increase this value, and passive voltage multiplier is a solution to this requirement. In this project, two passive voltage multipliers, namely, Modified Dickson (MDVM) and Mandal-Sarpeshkar (MSVM) voltage multipliers are designed and implemented. From a mere input power of 10 μW to 60 μW at 13.56 MHz, the voltage multipliers effectively increased the output voltage to 905 mV to 2.128 V and 1.114 V to 3.609 V for MDVM and MSVM, respectively, given a supply voltage of 1 V and a capacitive load of 30 pF. All designs are implemented using 90 nm CMOS process.
TENCON 2011 - 2011 IEEE Region 10 Conference, 2011
This project is an implementation of a runtime memory simulator with a compiler-assembler for the... more This project is an implementation of a runtime memory simulator with a compiler-assembler for the ARM7 microprocessor with multi-core and floating point operation capability. Compiler support is extended to floating point computations. Also, the integrated development environment (IDE) features selective optimization for compilation. The target outputs are the assembly codes following the instruction set architecture (ISA) of the ARM7 and
Uploads
Papers by Christian Roque