Journal of Engineering Research and Reports
6(1): 1-9, 2019; Article no.JERR.49877
Design of Common-gate with Common-source
Active Balun for WiMAX Receiver Front-end
Frederick Ray I. Gomez1,2*, Maria Theresa G. De Leon1
and John Richard E. Hizon1
1
Microelectronics and Microprocessors Laboratory, Electrical and Electronics Engineering Institute
College of Engineering, University of the Philippines, Diliman, Quezon City, 1101, Philippines.
2
Central Engineering and Development NPI, Back-end Manufacturing and Technology
STMicroelectronics, Inc., Calamba City, Laguna, 4027, Philippines.
Authors’ contributions
This work was carried out in collaboration amongst the authors. All authors read, reviewed and
approved the final manuscript.
Article Information
DOI: 10.9734/JERR/2019/v6i116939
Editor(s):
(1) Dr. P. Elangovan, Associate Professor, Department of EEE, Sreenivasa Institute of Technology and Management Studies,
Chittoor, Andhra Pradesh, India.
Reviewers:
(1) Yuan-Tsung Chen, National Yunlin University of Science and Technology, Taiwan.
(2) Boyan Karapenev, Technical University of Gabrovo, Bulgaria.
Complete Peer review History: http://www.sdiarticle3.com/review-history/49877
Original Research Article
Received 12 April 2019
Accepted 27 June 2019
Published 02 July 2019
ABSTRACT
This paper presents a design and simulation study of a common-gate with common-source active
balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS)
process. The active balun design is intended for worldwide interoperability for microwave access
(WiMAX) application, with operating frequency of 5.8 GHz and supply voltage of 1 V.
Measurements are taken for parameters namely gain difference, phase difference, and noise
figure. The common-source active balun design achieved a minimal gain difference of 0.04 dB,
phase difference of 180 ± 1.5 degrees, and noise figure of 8.76 dB, which are comparable to past
active balun designs and researches. The design eventually achieved a low power consumption of
4.45 mW.
Keywords: Common-gate with common-source active balun; gain difference; phase difference;
WiMAX.
_____________________________________________________________________________________________________
*Corresponding author: Email: frederick-ray.gomez@st.com, f.i.gomez@ieee.org;
Gomez et al.; JERR, 6(1): 1-9, 2019; Article no.JERR.49877
1. INTRODUCTION
amplifier (LNA). It can also be used to supply
differential signal to a mixer. Fig. 2 shows the
active balun circuit as an intermediate block
between the LNA and the mixer. Note that the
configuration depends on the gain, noise figure
(NF), and linearity requirements of the system.
Since LNA is the first block in the receiver front
end, it is critically designed with high gain of at
least 25 dB and noise figure of less than 2 dB.
Based on past researches, active balun has
relatively high noise figure and lower gain
performance compared to LNA, hence cannot be
considered as the first block in the receiver frontend. Finally, the challenge is to design an active
balun as an intermediate block to allow the LNA’s
output to connect with a differential mixer’s input,
with performance conforming to the requirement
for the WiMAX receiver front-end.
The radio frequency (RF) front-end of a wireless
receiver is one critical part in many wireless
communication systems such as bluetooth,
wireless
fidelity
(WiFi),
and
worldwide
interoperability for microwave access (WiMAX).
A typical wireless receiver is shown in Fig. 1
diagram.
Some key RF front-end circuits are often
designed in differential configuration.
Fullydifferential approach is mostly preferred in RF
integrated circuit (RFIC) design due to its
advantages, particularly the high immunity to
common-mode noises, rejection to parasitic
couplings, and increased dynamic range [1-2]. In
order to supply input signal to differential circuits,
a building block capable of supplying balanced
differential signals is needed without sacrificing
the performance of the overall system in terms of
gain, noise figure, and linearity. Active balun
(balanced-unbalanced) is capable to perform the
necessary tasks.
2. ACTIVE BALUN DESIGN
In this research paper, a differential active balun
is designed and implemented in a standard 90nm complementary metal-oxide semiconductor
(CMOS) technology. The supply voltage (VDD)
for the design is set to 1 V. The lengths (L) of all
transistors are set to 100 nm, which is the
minimum allowed channel length for the
technology used. Transistor widths (W) are
carefully computed to ensure the operation of all
the transistors at saturation.
As mentioned
earlier, the paper deals with the design of active
baluns as intermediate block between LNA and
mixer in the WiMAX receiver front-end. Table 1
summarizes the target specifications of the active
balun design. These values are based from past
active balun researches [1-4] and from the
summary of parameters as per WiMAX
standard [5].
A balun circuit is a type of transformer that
converts signals that are single-ended or
unbalanced with respect to ground into signals
that are differential or balanced with respect to
ground, and vice versa. Baluns can be classified
as either active or passive baluns depending on
the devices used. Active baluns, although
unidirectional and more complex to implement,
are preferred over their passive counterparts
because they can produce gain, occupy less chip
area and can operate at higher frequencies [1-3].
Active balun circuit can be used as the first block
of the WiMAX receiver front-end to supply
differential signal to a differential low-noise
Fig. 1. Block diagram of a wireless receiver
2
Gomez et al.; JERR, 6(1): 1-9, 2019; Article no.JERR.49877
Fig. 2. Active balun as intermediate block between LNA and mixer
Table 1. Minimum target parameter values for the differential active balun design
Parameters
Frequency
Gain difference
Phase difference
Noise figure
Power consumption
Value
5.8 GHz
< 1 dB
180 ± 10 degrees
< 10 dB
< 10 mW
The common-gate with common-source active
balun in Fig. 3 is comprised of 2 amplifiers
namely common-gate amplifier M1 in the 1st
stage and common-source amplifier M2 in the
2nd stage. The input signal is fed into the drain
of M1 and into the gate of M2, while the outputs
are probed at the drains of M1 and M2. Load
resistors R1 and R2 dictate the output
voltages as well as the voltage gains of the
two output signals with respect to the input
signal.
Two most important parameters of the active
balun are the gain difference and phase
difference. Gain difference is the difference of
the gains from the two output nodes of the active
balun while the phase difference is the difference
between the phase of the non-inverting output
node (RFout1) and the phase of inverting output
node (RFout2) of the active balun. Noise figure
on the other hand, is the measure of the amount
signal-to-noise-ratio
(SNR)
degradation
introduced by the circuit as seen in the output.
Fig. 3. Schematic diagram of common-gate with common-source active balun
3
Gomez et al.; JERR, 6(1): 1-9, 2019; Article no.JERR.49877
to 0.6 V. To compute for the proper biasing of
transistor M2, with input voltage kept at minimum
allowed which is at 0.6 V,
Common-source topology exhibits a relatively
high input impedance while providing voltage
gain and requiring a minimal voltage headroom.
With this, it finds wide application in analog
circuits and its frequency response is of interest.
Common-gate topology exhibits no Miller
multiplication
of
capacitances,
potentially
achieving a wide band [6-7]. However, the low
input impedance may load the preceding stage.
Moreover, since the voltage drop across R1 is
typically maximized to obtain the required gain,
the DC (direct current) level of the input signal
must be quite low. With the two topologies
connected as such to function as an active balun,
one major challenge would be to generate
balanced gain for the two outputs RFout1 and
RFout2 with respect to the input signal RFin,
given that the input signal is fed into two different
transistor ports.
=
2=
=
+
2
→
=
1
1
> 2 ≥ 0.2
+ 0.2
2
= 0.6
= 0.6
−
→ (
≥
− 0) − 0.4 = 0.2
1=
=
→
+
2
1
=
1
> 1 ≥ 0.6
+ 0.6
2
= 0.8
2=
+
2
1=
+
2
= 0.4
= 0.2
(7)
(8)
=
=
+ 0.1
=
1
1
+ 0.4
+ 0.1
2
= 0.5
+ 0.5
2
(9)
= 0.55
(10)
(11)
= 0.75
+ 0.1
=1
(12)
With input DC (or bias) voltage (VIN) set to 0.5 V,
gmoverId could be derived for the two branches
or outputs.
=
=
(
−
)(1 +
)
(13)
=
=
(
−
)(1 +
)
(14)
=
=
Substituting the expression for the drain current
(IDS) of into gm expressions,
(1)
(2)
=
=
(3)
2
2
−
=
2
−
−
−
2
=
=
−
2
−
=
=
=
2
2
−
1
−
(15)
(16)
(17)
(18)
For low power design, higher gmoverId is
recommended. To achieve such, VIN and VBIAS
should be optimized. With VBIAS fixed, increasing
the VIN increases the efficiency of M1 in terms of
gmoverId1. On the other hand, increasing VIN
would decrease the efficiency of M2 in terms of
gmoverId1. Lowering the drain current or supply
current (IDS) would also mean lowering gm to
maintain the efficiency for low power
consumption. With this, there is a limit in the
effectiveness of optimizing the input voltage (VIN), bias voltage (VBIAS) and supply current (IDS) to
maximize the efficiency in terms of gmoverId.
(4)
With VIN as the source voltage (VS1) of transistor
M1, output DC voltage for RFout1 which is V1 (or
VRFout1) could be calculated for maximum output
swing.
> 1≥
) − 0.4
−
If overdrive voltage VOV is set to 100 mV for both
transistors M1 and M2, output swings for V1 and
V2 could be adjusted. Also, VIN and bias voltage
(VBIAS) for M2 could be lowered. Recalculations
are shown in Eq. (9) to (12).
Input bias voltage VRFin (or simply VIN) is the
same as the gate voltage (VG2) of M2 and the
source voltage (VS1) of M1. To satisfy the VDS2 ≥
VDSAT2 = VOV2, input voltage (VIN) should be
properly set. With threshold voltage (Vt) set to
400 mV,
=
→ (
≥
= 1.2
To achieve the maximum output swing for M2,
VRFout2 (or just V2) should be between supply
voltage (VDD) and the VDSAT or the overdrive
voltage (VOV) of the transistor, ensuring also that
the transistor operates at the saturation region.
With VDD = 1 V, and VOV set to 200 mV, the
output at RFout2 could swing from 0.2 V to 1 V.
With the said output swing range, output DC
voltage (or bias voltage) V2 is computed in Eq.
(1) to (2).
> 2≥
−
(5)
(6)
Maximum output swing could be achieved at
output DC voltage V1 set to 0.8 V and at V2 set
4
Gomez et al.; JERR, 6(1): 1-9, 2019; Article no.JERR.49877
of the active balun, and is considered as one of
the most important parameters of the active
balun design. Ideally, the gain difference of an
active balun should be zero in magnitude. The
responses in Figs. 4 and 5 for the gain and gain
difference, respectively, are determined using AC
(alternating current) analysis. Input bias voltage
is set at 0.45 V. Both transistors M1 and M2
satisfied the requirements for saturation region
condition.
Furthermore, the design is optimized to meet the
target performance specifications suitable for
WIMAX receiver, and is implemented in a
standard 90-nm CMOS process using Cadence
Virtuoso software [8], computer-aided design
(CAD) tool and an electronic design automation
(EDA) software tool. Table 2 summarized the
common-gate with common-source active balun
parameters.
3. RESULTS AND DISCUSSION
Common-gate with common-source active balun
is designed to achieve a gain of just above 0dB.
This is validated in the AC gain results in Fig. 4.
Gain difference in Fig. 5 is expected to be close
to zero since the gain response for the two
outputs is very close to each other.
The common-gate with common-source active
balun is characterized and designed to achieve
the target specifications. The extraction of all
device parameters for use in simulations is done
using Synopsys Star-RCXT [9]. Simulations of
the extracted view are done using Cadence
Design Systems software. The active balun is
designed to operate at 5.8 GHz, which is a
typical frequency for WiMAX applications.
Measurements in the simulation plots are taken
at 5.8 GHz.
3.2 Phase and Phase Difference
Another important parameter of an active balun
is the phase difference. Phase difference is the
difference between the phase of the noninverting output node and the phase of inverting
output node of the active balun. Figs. 6 and 7
show the AC analysis phase and phase
difference responses, with ideal input voltage
source.
3.1 Gain and Gain Difference
There are many types of power gain defined for
an amplifier, with the most commonly specified
and often the most useful – the transducer gain,
GT. It is defined as the ratio of the power
delivered to the load to the power available from
the source. Gain difference or gain error is the
difference of the gains from the two output nodes
The results are within the target specification for
the phase difference. AC analysis measurement
for phase difference is at 178.5 degrees at 5.8
GHz frequency of operation.
Fig. 4. Gain plot using AC analysis
5
Gomez et al.; JERR, 6(1): 1-9, 2019; Article no.JERR.49877
Table 2. Common-gate with common-source active balun parameters and expressions
Parameters
Input bias voltage
Output DC voltage for maximum swing
Input impedance
Output impedance, with resistor and capacitor
loads
Voltage gain, simplified (s = 0)
Value
0.5 V
0.75 V (RFout1), 0.55 V (RFout2)
1 / (gm1 + gmb1)
R1 || 1/sC1 (RFout1), R2 || 1/sC2 (RFout2)
(
(
Output noise voltage
Noise figure
10
10
)
(RFout1)
)
−
2 (RFout2)
[1 + (
) 1]
+
(1 +
1+
∙
1+
∙
(
2)
(RFout1)
(RFout2)
)
∙
∙
(RFout1)
(RFout2)
Fig. 5. Gain difference plot using AC analysis
3.3 Noise Figure
the output. Fig. 8 shows the noise figure result
using PSS+PNoise analysis.
Noise performance is an important design
consideration
since
it
determines
the
susceptibility of the active balun to unwanted
signal or noise [2,10]. One important design
parameters is the noise figure, which is a
measure of the amount of signal-to-noise-ratio
degradation introduced by the circuit as seen at
Noise figure of 7.199 dB and 8.762 dB for
RFout1 and RFout2 with respect to RFin are
generated using PSS+PNoise analysis [11] taken
at frequency of 5.8 GHz. The values conformed
to the noise figure requirement set for the active
balun design.
6
Gomez et al.; JERR, 6(1): 1-9, 2019; Article no.JERR.49877
Fig. 6. Phase plot using AC analysis
Fig. 7. Phase difference plot using AC analysis
Table 3. Performance summary of differential active balun
Parameters
Process/Technology
Supply voltage
Frequency
Gain difference
Phase difference
Noise figure
Power consumption
Value
90-nm CMOS
1V
5.8 GHz
0.040 dB
178.5 degrees
7.199 dB (RFout1), 8.762 dB (RFout2)
4.449 mW
7
Target
90-nm CMOS
1V
5.8 GHz
< 1 dB
180 ± 10 degrees
< 10 dB
< 10 mW
Gomez et al.; JERR, 6(1): 1-9, 2019; Article no.JERR.49877
Fig. 8. Noise figure plot
3.4 Results Summary
Future work and research could explore
designing active balun with high gain. Although it
will sacrifice the bandwidth, it can still be realized
at
lower
frequencies
for
practical
applications. One possible work would be to
integrate the active balun functionality on
the circuit design of a differential circuit like
that of the double-balanced mixer or differential
LNA.
Table 3 summarizes the performance of the
three active balun designs.
The common-gate with common-source active
balun design achieved a gain difference better
than 1 dB and a phase difference of 180 ± 10
degrees or better at frequency of 5.8 GHz. The
balun is affected with the input and output
loading since the circuit is designed with ideal
input voltage source and no termination ports
included. Low power consumption of at most
4.45 mW is achieved, comparable to other low
power designs in the past researches.
4. CONCLUSION
TIONS
AND
ACKNOWLEDGEMENT
The authors would like to extend sincerest
gratitude to the Department of Science and
Technology (DOST), the Philippine Council for
Advanced Science and Technology Research
and Development under DOST (DOSTPCASTRD), and the Engineering Research and
Development
for
Technology Consortium
(DOST-ERDT) for the great support.
The
authors would like to thank the Microelectronics
and Microprocessors Laboratory team of the
University of the Philippines for the technical
support during the course of the study. Author
F.R. Gomez would like to express sincere
gratitude to the STMicroelectronics Calamba
Central Engineering and Development Team
and the Management Team for the extensive
support.
RECOMMENDA-
A common-gate with common-source active
balun is designed and implemented in a standard
90-nm CMOS process, and carefully designed to
satisfy the WiMAX receiver requirement at 5.8
GHz. Simulation measurements are taken for
parameters such as gain, phase, gain difference,
phase difference, and noise figure.
The design achieved gain difference of 0.04 dB
and phase difference of 180 ± 1.5 degrees.
Noise figure performance is at around 7.2–8.76
dB, comparable to previous designs and
researches. Low power consumption of at most.
4.45 mW is achieved, comparable to other low
power designs.
COMPETING INTERESTS
Authors have
interests exist.
8
declared
that
no
competing
Gomez et al.; JERR, 6(1): 1-9, 2019; Article no.JERR.49877
REFERENCES
1.
2.
3.
4.
5.
6.
Azevedo F, Fortes F, Rosario MJ. A new
on-chip CMOS active balun integrated with
LNA,” 14th IEEE International Conference
on Electronics, Circuits and Systems.
2007;1213–1216.
Gomez FR, De Leon MT, Roque CR.
Active balun circuits for WiMAX receiver
front-end. TENCON 2010 – IEEE Region
10 Conference. 2010;1156-1161.
Hsu TT, Kuo CN. Low power 8-GHz ultrawideband active balun. Topical Meeting on
Silicon Monolithic Integrated Circuits in RF
Systems; 2006.
Kawashima M, Nakagawa T, Araki K. A
rd
novel broadband active balun. 33
European Microwave Conference. 2003;2:
495-498.
IEEE standard 802.16e-2005. Part 16: Air
interface for fixed and mobile broadband
wireless access systems, Amendment 2:
Physical and medium access control layers
for combined fixed and mobile operation in
licensed bands, and Corrigendum 1. IEEE
7.
8.
9.
10.
11.
Computer Society and IEEE Microwave
Theory and Techniques Society; 2006.
Razavi B. RF Microelectronics, 2nd ed.,
Prentice Hall Press, Upper Saddle River,
New Jersey, USA; 2011.
RJ Baker, CMOS circuit design, layout,
and simulation, 3rd edition, IEEE Press,
New Jersey, USA, John Wiley & Sons,
Inc., New Jersey, USA; 2010.
Cadence design systems, Inc. Custom IC /
analog / RF design – circuit design.
Available:https://www.cadence.com/conten
t/ cadence-www/global/en_US/home/tools/
custom-ic-analog-rf-design/circuitdesign.html
Synopsys, Inc. Star RC – parasitic
extraction.
Available:https://www.synopsys.com/imple
mentation-and-signoff /signoff /starrc.html
Gomez FR. Electronic noise and noise
analysis. UP EE 220 Analog IC Design
Course; 2008.
Cadence design systems, Inc. LNA design
using Spectre RF. Application Note,
product version 6.0; 2005.
© 2019 Gomez et al.; This is an Open Access article distributed under the terms of the Creative Commons Attribution License
(http://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium,
provided the original work is properly cited.
Peer-review history:
The peer review history for this paper can be accessed here:
http://www.sdiarticle3.com/review-history/49877
9