As the data rates of high-speed I/O interfaces with large numbers of I/Os increase beyond 5Gb/s i... more As the data rates of high-speed I/O interfaces with large numbers of I/Os increase beyond 5Gb/s it becomes increasingly difficult to separate out the effects of silicon performance from the interaction of package, socket and test fixture characteristics. This work discusses the need for separating silicon measurements from the channel measurements of a packaged device, the challenges of making these
... 1: Wavecrest, 1735 Technology Dr., Suite 400, San Jose, CA 951 10, mli@wavecrest.com 2: Intel... more ... 1: Wavecrest, 1735 Technology Dr., Suite 400, San Jose, CA 951 10, mli@wavecrest.com 2: Intel, 1900 Prairie City Rd, Folsom, CA 95630, andy.martwick@intel.com 3: AMD, 80 ... Most clock recovery circuits have a low-pass characteristic, such as PLL-basd clock recovery circuits ...
As the data rates of high-speed I/O interfaces with large numbers of I/Os increase beyond 5Gb/s i... more As the data rates of high-speed I/O interfaces with large numbers of I/Os increase beyond 5Gb/s it becomes increasingly difficult to separate out the effects of silicon performance from the interaction of package, socket and test fixture characteristics. This work discusses the need for separating silicon measurements from the channel measurements of a packaged device, the challenges of making these
... 1: Wavecrest, 1735 Technology Dr., Suite 400, San Jose, CA 951 10, mli@wavecrest.com 2: Intel... more ... 1: Wavecrest, 1735 Technology Dr., Suite 400, San Jose, CA 951 10, mli@wavecrest.com 2: Intel, 1900 Prairie City Rd, Folsom, CA 95630, andy.martwick@intel.com 3: AMD, 80 ... Most clock recovery circuits have a low-pass characteristic, such as PLL-basd clock recovery circuits ...
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