Field Programmable Gate Arrays (FPGAs) are semiconductor devices that contain logic components co... more Field Programmable Gate Arrays (FPGAs) are semiconductor devices that contain logic components connected by a regular, hierarchical programmable interconnect system. The distinguishing characteristic of FPGAs is their on-filed programmability which allows the logic functionality of an FPGA to be re-programmed even after the manufacturing process. FPGAs are used for rapid prototyping of digital circuits. The design and test of digital systems are time efficient and cost-effective with FPGAs. The logic components in the FPGA mostly consists of memory elements such as registers or even complete blocks of memory that can be configured to hold any desired state. The hierarchical interconnect system is also programmable which allows the logic components to be connected in a variety of network configurations. Therefore the re-programmability of FPGAs is achieved by a fixed underlying architecture, which does not cater to any particular logic circuit. This lets FPGAs have a lower non-recurring cost, shorter design cycle and enables them to be re-programmed in the field to circumvent manufacturing defects. This chapter discuses about the FPGA building blocks and how they are interconnected to form a flexible digital prototyping and design platform.
The semiconductor industries current enthusiasm for 3D-ICs is widespread and well warranted, but ... more The semiconductor industries current enthusiasm for 3D-ICs is widespread and well warranted, but designing those 3D devices presents a challenge. Normal 2D design tools are thoroughly honed and refined over many years, nonetheless fail to address some of the critical issues of 3D-IC design. A new 3D-IC design process is evolving gradually from the 2D heritage. Today there are tools to handle a complete back-end flow and strides are being made to enable true 3D design and implementation using TSVs. In this chapter we discuss the design algorithms and techniques to develop 3D physical design tools and use of these tools to design and fabricate 3D stacked Tree-based FPGAs. This chapter starts with development of VHDL code generator and continue to the development 3D layouts of Tree-based FPGA using the 3D physical design tools developed for 3D FPGA design. A new CAD tool set for 3D physical design and verification based on Global Foundries 130 nm technology node modified to use Tezzaron’s TSV technology is also developed and presented in this chapter. Through this chapter we addressed few specific issues 3D designers often encounter dealing with tools that are not specifically designed to meet their needs. We also presented few additional 3D design support tools such as 3D LVS/DRC to verify the LVS of the partitioned and merged 3D designs.
2015 6th Asia Symposium on Quality Electronic Design (ASQED), 2015
In this paper we propose a three-dimensional (3D) interconnect network implementation based on a ... more In this paper we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Trees (MoT) topology for FPGA architecture design. To obtain the optimal MoT-based interconnect structure, the routing architecture of the 2D MoT-based FPGA is modified to include long routing segments that span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, a 2.5D or 3D high density MoT FPGAs can be designed. To design 3D multi-stacked MoT-based FPGAs, the 2D MoT FPGA is cut into two or more equal sections by adjusting the long wire span. The long wire segments are realized using 3D through silicon via (TSV). To design 2.5D interposer-based multi-FPGAs, we increase the number of cuts and apply appropriate optimization models to scale down the number of long wires and horizontal inter-FPGA interposer wires. Using our 2.5/3D design and simulation CAD flow, we demonstrate the speed and area of 3D MoT-based FPGA architecture is improved by 54% and 41% respectively in comparison to 3D Mesh-based FPGA.
Modern FPGAs have become a viable alternative to cell-based design technology by providing re-con... more Modern FPGAs have become a viable alternative to cell-based design technology by providing re-configurable computing platforms with improved performance and higher density using 3D integration technology. While the re-configurability provides flexibility, FPGAs also lead to area and performance overhead in comparison to cell-based custom integrated circuits (ICs). Thus to combine the advantages of both FPGAs and custom ICs, modern 3D heterogeneous FPGAs emerged as an attractive solution for system-on-chip implementations. The modern FPGAs include design components such as digital signal processors, on chip memory blocks, multipliers, adders, and entire processors. In this chapter our primary focus is on teaching the development of 3D FPGA tools and technologies and the validation of architecture exploration tools and optimization methodologies by using custom designed 3D homogeneous and heterogeneous Tree-based FPGAs.
2016 International Conference on High Performance Computing & Simulation (HPCS), 2016
The interconnect structure in common FPGA architectures is generally designed to maximize logic u... more The interconnect structure in common FPGA architectures is generally designed to maximize logic utilization. A fully populated routing interconnect is simple and provides high flexibility at the cost of power and area overhead. Moreover, the utilization rate of interconnect switches is extremely low. In this paper, we aim to explore new cluster-based mesh FPGA architectures with depopulated routing network. First, we propose a Depopulated FPGA (DFPGA) architecture with depopulated intra-cluster and inter-cluster interconnects. Based on a comparison with a common Mesh architecture, we note that power and area are improved respectively by an average of 23% and 30%. However, these improvements are obtained at the cost of wiring complexity, congestion and low flexibility to route complex circuits. To alleviate those weaknesses, we propose to populate inter-cluster interconnect by using hierarchy. We show experimentally that the second proposed FPGA architecture with Multilevel Switch blocks (MS-FPGA) has a good routability and interesting power consumption and area density compared to the common cluster-based mesh FPGA. Moreover, additional switches used in the hierarchical inter-cluster interconnect of the MSFPGA are compensated with a better flexibility. Unlike DFPGA, MS-FPGA can deal with complex circuits.
The primary focus of this chapter is to demonstrate a 3D integration scheme to partition and opti... more The primary focus of this chapter is to demonstrate a 3D integration scheme to partition and optimize the multilevel programmable interconnect network of Tree-based FPGA based on Butterfly-Fat-Tree network topology, where TSVs are incorporated in active layers of the 3D chip. This chapter describes the details of the architecture of 3D FPGAs and state-of-the-art 3D technology for Mesh-based FPGAs. To take advantage of 3D integrated circuits, it should be investigated how FPGA should be physically partitioned into different active layers. Proper physical partitioning has a great impact on the performance improvement of the system. This chapter discuss different partitioning schemes and design techniques and associated 3D CAD tools of 3D FPGAs.
In this paper, we present an improved Mesh of Clusters (MoC) architecture with new hierarchical S... more In this paper, we present an improved Mesh of Clusters (MoC) architecture with new hierarchical Switch Box (SB) topology and depopulated intra-cluster interconnect with flexible Rent’s parameter. The aim of this paper is to explore the effect of different architecture parameters like architecture Rent’s, design Rent’s and channel width. Then, we analyze how these factors interact and the way to tune them to satisfy various specific application constraints and quality metrics like power consumption and area. The proposed exploration methodology unifies two procedures which are analytical method based on Rent’s rule modeling and experimental method based on benchmarks circuits implementation. A comparison with VPR mesh architecture shows gains in terms power and area equal respectively to 30% and 32%.
A 3D-IC system consists of disparate materials with considerably different thermal properties inc... more A 3D-IC system consists of disparate materials with considerably different thermal properties including semiconductor, metal, dielectric, and possibly polymer layers used for inter-plane bonding. Although the power consumption of these circuits is expected to decrease due to the considerably shorter interconnects, the power density increases since there is a greater number of devices per unit volume as compared to a 2D circuit. Heat transfer analysis in 3D-ICs is complicated by the presence of multiple heat sources and the introduction of new thermal resistances posed by inter-die materials including interface resistances whose values are not readily available. In this chapter we present a fast and accurate 3D thermal model developed for an n-tier 3D stacked Tree-based FPGA chip using 3D R-C mesh-based model. The design and implementation of 3D thermal analysis model depends on the characteristics materials and layers used to manufacture VLSI chips.
2014 International 3D Systems Integration Conference (3DIC), 2014
In this study, we propose a three-dimensional (3D) interconnect network implementation based on a... more In this study, we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Clusters (MoC) topology for FPGA architecture design. Design and experimental setup is developed to demonstrate the improvement in performance, power and area of 2.5D and 3D MoC-based FPGA architecture. MoC starts with a mesh of nodes and builds a separate hierarchical network along each row and column in the mesh. To obtain the optimal MoC programmable interconnect structure with high performance and density, the routing architecture of the 2D MoC-based FPGA is modified to include long routing segments which span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, we can design and build 2.5D and 3D high density MoC FPGAs. To design 3D MoC-based FPGAs, we cut the 2D MoC FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV) technology. To design 2.5D interposer based multi-FPGA architecture, we use the same principle of cuts and we adjust the long wires span to remain within die connections. However, we apply constraints at cutline location to reduce the die to die interposer connections. A 3D physical design CAD for MoC-based FPGA is developed using Global Foundries 130nm technology node modified to use TSV designs from Tezzaron Semiconductor inc. Using our 3D design and simulation tool flow developed for MoC-based FPGA, we demonstrate that the speed, power and area of 3D MoC-based FPGA architecture are improved respectively by 35%, 21% and 47% in comparison to 2D MoC-based FPGA.
2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014
ABSTRACT Nowadays, higher resolutions and faster processing time are more and more demanded in th... more ABSTRACT Nowadays, higher resolutions and faster processing time are more and more demanded in the field of video applications. Thus, algorithmic complexity of the encoder and its performances are the main penalties for such requirements. Recent woks show the efficiency of using the Multiprocessor System on Chip (MPSoC) technology to overcome the shortcomings of real-time processing with a single processor. We contribute to this challenge by proposing a MPSoC architecture for the intra prediction encoding chain, which is an important part of the H.264/AVC video standard. This MPSoC architecture is based on Component Level Parallelism (CLP) approach. This approach is tested and evaluated on SoCLib platform for virtual prototyping of MPSoC architectures. Experimental results show a gain of 32% in encoding speed when using two processors (CPUs), and enabling minimum memory size and MPSoC surface.
2016 Euromicro Conference on Digital System Design (DSD), 2016
Multi-FPGA prototyping, because of its low cost, high speed, and real world testing is quite popu... more Multi-FPGA prototyping, because of its low cost, high speed, and real world testing is quite popular today for pre-silicon verification of increasingly complex designs. In this work, we present a novel exploration flow that is used to analyze and optimize the multi-FPGA based prototyping of complex digital designs. In this flow, an end-to-end experience starting from benchmark generation to optimized inter-FPGA routing is given. For inter-FPGA routing, timing-driven approach is used instead of previously used routability-driven approach. Ten large designs are generated using generic tools of the flow and then effect of number of FPGAs on board, number of inter-FPGA tracks is observed on the performance of generated designs. Extensive experimentation reveals that FPGA board with six FPGAs gives best system frequency results. Furthermore, execution time comparison between routability and timing-driven approach reveals that compared to routability-driven approach, timing-driven approach consumes, on average, 46% less time while giving same or better frequency results.
An Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can imple... more An Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at mutually exclusive times. An ASIF that is reduced from a heterogeneous FPGA is called as a Heterogeneous-ASIF. A Heterogeneous-ASIF can contain hard-block such as Multipliers, Adders, RAMS or even smaller Gates. A set of application circuits are efficiently placed and routed to minimize total routing switches required by the heterogeneous FPGA architecture. Different floor-planning techniques are used to optimize the position of hard-blocks on the FPGA architecture. Later, all unused routing switches are removed from the FPGA to generate a Heterogeneous-ASIF. This work shows that a standard-cell based Heterogeneous-ASIF using Multipliers, Adders and Look-Up Tables for a set of 10 opencores application circuits is 85% smaller in area than a single-driver FPGA using the same type of blocks. This Heterogeneous-ASIF is only 24% larger than the sum of areas of their standard-cell based ASIC versions. If the Look-Up Tables are replaced by a set of repeatedly used hard logic gates (such as AND gate, OR gate, Flip- Flops etc), the ASIF becomes 89% smaller than the FPGA and 3% smaller than the sum of ASICs. The area gap between ASIF and sum of ASICs can be further reduced if repeatedly used groups of standard-cell logic gates in an ASIF are designed in full-custom. One of the major advantages of an ASIF is that just like an FPGA, an ASIF can also be reprogrammed to execute new or modified circuits, but at a very limited scale. A new CAD flow is presented to map application circuits on an ASIF.
In this paper we investigate the design of macro-cell generators of division and square root floa... more In this paper we investigate the design of macro-cell generators of division and square root floating-point operators. The number representation used in our operators is the IEEE-754-1985 standard for binary floating-point numbers. The design and implementation of the generators rely on a powerful multiview layout synthesis tool called GenOptim. This CAD tool is able to output a set of different
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that contain logic components co... more Field Programmable Gate Arrays (FPGAs) are semiconductor devices that contain logic components connected by a regular, hierarchical programmable interconnect system. The distinguishing characteristic of FPGAs is their on-filed programmability which allows the logic functionality of an FPGA to be re-programmed even after the manufacturing process. FPGAs are used for rapid prototyping of digital circuits. The design and test of digital systems are time efficient and cost-effective with FPGAs. The logic components in the FPGA mostly consists of memory elements such as registers or even complete blocks of memory that can be configured to hold any desired state. The hierarchical interconnect system is also programmable which allows the logic components to be connected in a variety of network configurations. Therefore the re-programmability of FPGAs is achieved by a fixed underlying architecture, which does not cater to any particular logic circuit. This lets FPGAs have a lower non-recurring cost, shorter design cycle and enables them to be re-programmed in the field to circumvent manufacturing defects. This chapter discuses about the FPGA building blocks and how they are interconnected to form a flexible digital prototyping and design platform.
The semiconductor industries current enthusiasm for 3D-ICs is widespread and well warranted, but ... more The semiconductor industries current enthusiasm for 3D-ICs is widespread and well warranted, but designing those 3D devices presents a challenge. Normal 2D design tools are thoroughly honed and refined over many years, nonetheless fail to address some of the critical issues of 3D-IC design. A new 3D-IC design process is evolving gradually from the 2D heritage. Today there are tools to handle a complete back-end flow and strides are being made to enable true 3D design and implementation using TSVs. In this chapter we discuss the design algorithms and techniques to develop 3D physical design tools and use of these tools to design and fabricate 3D stacked Tree-based FPGAs. This chapter starts with development of VHDL code generator and continue to the development 3D layouts of Tree-based FPGA using the 3D physical design tools developed for 3D FPGA design. A new CAD tool set for 3D physical design and verification based on Global Foundries 130 nm technology node modified to use Tezzaron’s TSV technology is also developed and presented in this chapter. Through this chapter we addressed few specific issues 3D designers often encounter dealing with tools that are not specifically designed to meet their needs. We also presented few additional 3D design support tools such as 3D LVS/DRC to verify the LVS of the partitioned and merged 3D designs.
2015 6th Asia Symposium on Quality Electronic Design (ASQED), 2015
In this paper we propose a three-dimensional (3D) interconnect network implementation based on a ... more In this paper we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Trees (MoT) topology for FPGA architecture design. To obtain the optimal MoT-based interconnect structure, the routing architecture of the 2D MoT-based FPGA is modified to include long routing segments that span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, a 2.5D or 3D high density MoT FPGAs can be designed. To design 3D multi-stacked MoT-based FPGAs, the 2D MoT FPGA is cut into two or more equal sections by adjusting the long wire span. The long wire segments are realized using 3D through silicon via (TSV). To design 2.5D interposer-based multi-FPGAs, we increase the number of cuts and apply appropriate optimization models to scale down the number of long wires and horizontal inter-FPGA interposer wires. Using our 2.5/3D design and simulation CAD flow, we demonstrate the speed and area of 3D MoT-based FPGA architecture is improved by 54% and 41% respectively in comparison to 3D Mesh-based FPGA.
Modern FPGAs have become a viable alternative to cell-based design technology by providing re-con... more Modern FPGAs have become a viable alternative to cell-based design technology by providing re-configurable computing platforms with improved performance and higher density using 3D integration technology. While the re-configurability provides flexibility, FPGAs also lead to area and performance overhead in comparison to cell-based custom integrated circuits (ICs). Thus to combine the advantages of both FPGAs and custom ICs, modern 3D heterogeneous FPGAs emerged as an attractive solution for system-on-chip implementations. The modern FPGAs include design components such as digital signal processors, on chip memory blocks, multipliers, adders, and entire processors. In this chapter our primary focus is on teaching the development of 3D FPGA tools and technologies and the validation of architecture exploration tools and optimization methodologies by using custom designed 3D homogeneous and heterogeneous Tree-based FPGAs.
2016 International Conference on High Performance Computing & Simulation (HPCS), 2016
The interconnect structure in common FPGA architectures is generally designed to maximize logic u... more The interconnect structure in common FPGA architectures is generally designed to maximize logic utilization. A fully populated routing interconnect is simple and provides high flexibility at the cost of power and area overhead. Moreover, the utilization rate of interconnect switches is extremely low. In this paper, we aim to explore new cluster-based mesh FPGA architectures with depopulated routing network. First, we propose a Depopulated FPGA (DFPGA) architecture with depopulated intra-cluster and inter-cluster interconnects. Based on a comparison with a common Mesh architecture, we note that power and area are improved respectively by an average of 23% and 30%. However, these improvements are obtained at the cost of wiring complexity, congestion and low flexibility to route complex circuits. To alleviate those weaknesses, we propose to populate inter-cluster interconnect by using hierarchy. We show experimentally that the second proposed FPGA architecture with Multilevel Switch blocks (MS-FPGA) has a good routability and interesting power consumption and area density compared to the common cluster-based mesh FPGA. Moreover, additional switches used in the hierarchical inter-cluster interconnect of the MSFPGA are compensated with a better flexibility. Unlike DFPGA, MS-FPGA can deal with complex circuits.
The primary focus of this chapter is to demonstrate a 3D integration scheme to partition and opti... more The primary focus of this chapter is to demonstrate a 3D integration scheme to partition and optimize the multilevel programmable interconnect network of Tree-based FPGA based on Butterfly-Fat-Tree network topology, where TSVs are incorporated in active layers of the 3D chip. This chapter describes the details of the architecture of 3D FPGAs and state-of-the-art 3D technology for Mesh-based FPGAs. To take advantage of 3D integrated circuits, it should be investigated how FPGA should be physically partitioned into different active layers. Proper physical partitioning has a great impact on the performance improvement of the system. This chapter discuss different partitioning schemes and design techniques and associated 3D CAD tools of 3D FPGAs.
In this paper, we present an improved Mesh of Clusters (MoC) architecture with new hierarchical S... more In this paper, we present an improved Mesh of Clusters (MoC) architecture with new hierarchical Switch Box (SB) topology and depopulated intra-cluster interconnect with flexible Rent’s parameter. The aim of this paper is to explore the effect of different architecture parameters like architecture Rent’s, design Rent’s and channel width. Then, we analyze how these factors interact and the way to tune them to satisfy various specific application constraints and quality metrics like power consumption and area. The proposed exploration methodology unifies two procedures which are analytical method based on Rent’s rule modeling and experimental method based on benchmarks circuits implementation. A comparison with VPR mesh architecture shows gains in terms power and area equal respectively to 30% and 32%.
A 3D-IC system consists of disparate materials with considerably different thermal properties inc... more A 3D-IC system consists of disparate materials with considerably different thermal properties including semiconductor, metal, dielectric, and possibly polymer layers used for inter-plane bonding. Although the power consumption of these circuits is expected to decrease due to the considerably shorter interconnects, the power density increases since there is a greater number of devices per unit volume as compared to a 2D circuit. Heat transfer analysis in 3D-ICs is complicated by the presence of multiple heat sources and the introduction of new thermal resistances posed by inter-die materials including interface resistances whose values are not readily available. In this chapter we present a fast and accurate 3D thermal model developed for an n-tier 3D stacked Tree-based FPGA chip using 3D R-C mesh-based model. The design and implementation of 3D thermal analysis model depends on the characteristics materials and layers used to manufacture VLSI chips.
2014 International 3D Systems Integration Conference (3DIC), 2014
In this study, we propose a three-dimensional (3D) interconnect network implementation based on a... more In this study, we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Clusters (MoC) topology for FPGA architecture design. Design and experimental setup is developed to demonstrate the improvement in performance, power and area of 2.5D and 3D MoC-based FPGA architecture. MoC starts with a mesh of nodes and builds a separate hierarchical network along each row and column in the mesh. To obtain the optimal MoC programmable interconnect structure with high performance and density, the routing architecture of the 2D MoC-based FPGA is modified to include long routing segments which span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, we can design and build 2.5D and 3D high density MoC FPGAs. To design 3D MoC-based FPGAs, we cut the 2D MoC FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV) technology. To design 2.5D interposer based multi-FPGA architecture, we use the same principle of cuts and we adjust the long wires span to remain within die connections. However, we apply constraints at cutline location to reduce the die to die interposer connections. A 3D physical design CAD for MoC-based FPGA is developed using Global Foundries 130nm technology node modified to use TSV designs from Tezzaron Semiconductor inc. Using our 3D design and simulation tool flow developed for MoC-based FPGA, we demonstrate that the speed, power and area of 3D MoC-based FPGA architecture are improved respectively by 35%, 21% and 47% in comparison to 2D MoC-based FPGA.
2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014
ABSTRACT Nowadays, higher resolutions and faster processing time are more and more demanded in th... more ABSTRACT Nowadays, higher resolutions and faster processing time are more and more demanded in the field of video applications. Thus, algorithmic complexity of the encoder and its performances are the main penalties for such requirements. Recent woks show the efficiency of using the Multiprocessor System on Chip (MPSoC) technology to overcome the shortcomings of real-time processing with a single processor. We contribute to this challenge by proposing a MPSoC architecture for the intra prediction encoding chain, which is an important part of the H.264/AVC video standard. This MPSoC architecture is based on Component Level Parallelism (CLP) approach. This approach is tested and evaluated on SoCLib platform for virtual prototyping of MPSoC architectures. Experimental results show a gain of 32% in encoding speed when using two processors (CPUs), and enabling minimum memory size and MPSoC surface.
2016 Euromicro Conference on Digital System Design (DSD), 2016
Multi-FPGA prototyping, because of its low cost, high speed, and real world testing is quite popu... more Multi-FPGA prototyping, because of its low cost, high speed, and real world testing is quite popular today for pre-silicon verification of increasingly complex designs. In this work, we present a novel exploration flow that is used to analyze and optimize the multi-FPGA based prototyping of complex digital designs. In this flow, an end-to-end experience starting from benchmark generation to optimized inter-FPGA routing is given. For inter-FPGA routing, timing-driven approach is used instead of previously used routability-driven approach. Ten large designs are generated using generic tools of the flow and then effect of number of FPGAs on board, number of inter-FPGA tracks is observed on the performance of generated designs. Extensive experimentation reveals that FPGA board with six FPGAs gives best system frequency results. Furthermore, execution time comparison between routability and timing-driven approach reveals that compared to routability-driven approach, timing-driven approach consumes, on average, 46% less time while giving same or better frequency results.
An Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can imple... more An Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at mutually exclusive times. An ASIF that is reduced from a heterogeneous FPGA is called as a Heterogeneous-ASIF. A Heterogeneous-ASIF can contain hard-block such as Multipliers, Adders, RAMS or even smaller Gates. A set of application circuits are efficiently placed and routed to minimize total routing switches required by the heterogeneous FPGA architecture. Different floor-planning techniques are used to optimize the position of hard-blocks on the FPGA architecture. Later, all unused routing switches are removed from the FPGA to generate a Heterogeneous-ASIF. This work shows that a standard-cell based Heterogeneous-ASIF using Multipliers, Adders and Look-Up Tables for a set of 10 opencores application circuits is 85% smaller in area than a single-driver FPGA using the same type of blocks. This Heterogeneous-ASIF is only 24% larger than the sum of areas of their standard-cell based ASIC versions. If the Look-Up Tables are replaced by a set of repeatedly used hard logic gates (such as AND gate, OR gate, Flip- Flops etc), the ASIF becomes 89% smaller than the FPGA and 3% smaller than the sum of ASICs. The area gap between ASIF and sum of ASICs can be further reduced if repeatedly used groups of standard-cell logic gates in an ASIF are designed in full-custom. One of the major advantages of an ASIF is that just like an FPGA, an ASIF can also be reprogrammed to execute new or modified circuits, but at a very limited scale. A new CAD flow is presented to map application circuits on an ASIF.
In this paper we investigate the design of macro-cell generators of division and square root floa... more In this paper we investigate the design of macro-cell generators of division and square root floating-point operators. The number representation used in our operators is the IEEE-754-1985 standard for binary floating-point numbers. The design and implementation of the generators rely on a powerful multiview layout synthesis tool called GenOptim. This CAD tool is able to output a set of different
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