2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 2007
Vower consumption has become increasingly more important with the advent mobile and wireless devi... more Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design flow that
2014 24th International Conference Radioelektronika, 2014
ABSTRACT A novel impedance fault simulations methodology is presented in this paper. This methodo... more ABSTRACT A novel impedance fault simulations methodology is presented in this paper. This methodology is based on an equation that calculates two-point impedance using the eigenvalues and eigenvectors of the circuit's nodal admittance matrix. This approach is applicable to active and passive circuits in both DC and AC domains. Possible applications of the proposed methods in the design of integrated circuits are presented as well.
A novel approach to the dynamic supply current sensing based on the measurement of voltage drop a... more A novel approach to the dynamic supply current sensing based on the measurement of voltage drop across a parasitic resistance of the supply voltage metal line is presented. Then, auto-zero technique for voltage comparator offset cancellation, which provides very accurate and sensitive low voltage measurement is proposed. Therefore, we may use this as a current monitor for dynamic current testing of mixed-signal circuits without any additional element necessarily connected in series with the power supply line. The proposed current monitor was designed in a standard 0.35µm CMOS technology. Feasibility of this approach was investigated for a wide temperature range and process variations using Monte-Carlo analysis.
This paper deals with the design of elementary building blocks of frequency synthesizer (Phase-Lo... more This paper deals with the design of elementary building blocks of frequency synthesizer (Phase-Locked Loop) - phase detector and voltage-controlled oscillator (VCO) in the radio frequency region (RF). They have been designed in the standard AMS 0.35µm CMOS technology, with analysis and optimisation performed using CADENCE tools (SpectreRF) and ASITIC software. The VCO was experimentally realised as test chip with A-MOS capacitance tuning circuit elements. The proposed LC oscillator is implemented in double- cross topology with the supply voltage of 2.7 V. Additionally, also a phase comparator design is discussed, implemented and investigated, as a very important part of the PLL structure for RF applications. The low phase noise PLL implementation is also presented.
ABSTRACT A new on-chip oscillation test strategy for analog and mixed-signal circuits is presente... more ABSTRACT A new on-chip oscillation test strategy for analog and mixed-signal circuits is presented. In the proposed method, onchip Schmitt trigger is used as the on-chip frequency reference to compensate the influence of process parameter variations. Furthermore, this solution also brings the possibility to implement Oscillation-based Built-In Self-Test (OBIST) for analog and mixed-signal integrated circuits. The proposed OBIST strategy has been experimentally applied to active analog integrated filters, and its efficiency in detecting hard-detectable catastrophic faults is presented. To demonstrate applicability of the proposed method also in nanoscale technologies, the method has been used to test a noninverting amplifier designed in 90 nm CMOS technology. Consequently, the impact of scaling was analyzed and the method efficiency in covering catastrophic faults achieved for 0.35 μm and 90 nm CMOS technology were compared.
Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2007
Vower consumption has become increasingly more important with the advent mobile and wireless devi... more Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design flow that
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 2007
Vower consumption has become increasingly more important with the advent mobile and wireless devi... more Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design flow that
2014 24th International Conference Radioelektronika, 2014
ABSTRACT A novel impedance fault simulations methodology is presented in this paper. This methodo... more ABSTRACT A novel impedance fault simulations methodology is presented in this paper. This methodology is based on an equation that calculates two-point impedance using the eigenvalues and eigenvectors of the circuit's nodal admittance matrix. This approach is applicable to active and passive circuits in both DC and AC domains. Possible applications of the proposed methods in the design of integrated circuits are presented as well.
A novel approach to the dynamic supply current sensing based on the measurement of voltage drop a... more A novel approach to the dynamic supply current sensing based on the measurement of voltage drop across a parasitic resistance of the supply voltage metal line is presented. Then, auto-zero technique for voltage comparator offset cancellation, which provides very accurate and sensitive low voltage measurement is proposed. Therefore, we may use this as a current monitor for dynamic current testing of mixed-signal circuits without any additional element necessarily connected in series with the power supply line. The proposed current monitor was designed in a standard 0.35µm CMOS technology. Feasibility of this approach was investigated for a wide temperature range and process variations using Monte-Carlo analysis.
This paper deals with the design of elementary building blocks of frequency synthesizer (Phase-Lo... more This paper deals with the design of elementary building blocks of frequency synthesizer (Phase-Locked Loop) - phase detector and voltage-controlled oscillator (VCO) in the radio frequency region (RF). They have been designed in the standard AMS 0.35µm CMOS technology, with analysis and optimisation performed using CADENCE tools (SpectreRF) and ASITIC software. The VCO was experimentally realised as test chip with A-MOS capacitance tuning circuit elements. The proposed LC oscillator is implemented in double- cross topology with the supply voltage of 2.7 V. Additionally, also a phase comparator design is discussed, implemented and investigated, as a very important part of the PLL structure for RF applications. The low phase noise PLL implementation is also presented.
ABSTRACT A new on-chip oscillation test strategy for analog and mixed-signal circuits is presente... more ABSTRACT A new on-chip oscillation test strategy for analog and mixed-signal circuits is presented. In the proposed method, onchip Schmitt trigger is used as the on-chip frequency reference to compensate the influence of process parameter variations. Furthermore, this solution also brings the possibility to implement Oscillation-based Built-In Self-Test (OBIST) for analog and mixed-signal integrated circuits. The proposed OBIST strategy has been experimentally applied to active analog integrated filters, and its efficiency in detecting hard-detectable catastrophic faults is presented. To demonstrate applicability of the proposed method also in nanoscale technologies, the method has been used to test a noninverting amplifier designed in 90 nm CMOS technology. Consequently, the impact of scaling was analyzed and the method efficiency in covering catastrophic faults achieved for 0.35 μm and 90 nm CMOS technology were compared.
Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2007
Vower consumption has become increasingly more important with the advent mobile and wireless devi... more Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design flow that
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