This paper discusses the limitation of both Sequence Covering Array (SCA) and Covering Array (CA)... more This paper discusses the limitation of both Sequence Covering Array (SCA) and Covering Array (CA) for testing reactive system when the order of parameter-values is sensitive. In doing so, this paper proposes a new model to take the sequence values into consideration. Accordingly, by superimposing the CA onto SCA yields another type of combinatorial test suite termed Multi-Valued Sequence Covering Array (MVSCA) in a more generalized form. This superimposing is a challenging process due to NP-Hardness for both SCA and CA. Motivated by such a challenge, this paper presents the MVSCA with a working illustrative example to show the similarities and differences among combinatorial testing methods. Consequently, the MVSCA is a new trend that can be a research vehicle for researchers to develop new and/or modify existing combinatorial strategies to deal with the combinatorial explosion problem raised by the MVSCA.
Software testing is a vital part of the software development life cycle. In many cases, the syste... more Software testing is a vital part of the software development life cycle. In many cases, the system under test has more than one input making the testing efforts for every exhaustive combination impossible (i.e. the time of execution of the test case can be outrageously long). Combinatorial testing offers an alternative to exhaustive testing via considering the interaction of input values for every t-way combination between parameters. Combinatorial testing can be divided into three types which are uniform strength interaction, variable strength interaction and input-output based relation (IOR). IOR combinatorial testing only tests for the important combinations selected by the tester. Most of the researches in combinatorial testing applied the uniform and the variable interaction strength, however, there is still a lack of work addressing IOR. In this paper, a Jaya algorithm is proposed as an optimization algorithm engine to construct a test list based on IOR in the proposed combina...
Online Examination is an essential ingredient in electronic and interactive learning, however, in... more Online Examination is an essential ingredient in electronic and interactive learning, however, in educational environment most of examinations are done in the classical paper-based way due to the lack of resumption capability when power/network/physical computer's component failures. For this reason, adopting and developing an online examination system acts as an active research area in recent years. This paper reviews the state-of-the-art and the-art-of-the-practice for nine general-purpose online examination systems found in the literature, as well as, some dedicated industrial systems based on seven elected intertwined features; namely: secure login, resumption capability, multi-instructor, random question selection, random questions distribution, random choice distribution, and portability implementation method. Even though, the implementation of these systems is promising, however, these systems have some bleeding points. For instance, by practicing the existing examination...
2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA), 2010
Abstract This paper discusses the state of the art of applying combinatorial interaction testing ... more Abstract This paper discusses the state of the art of applying combinatorial interaction testing (CIT) in conjunction with mutation testing for hardware testing. In addition, the paper discusses the art of the practice of applying CIT in normal and cumulative mode in order to derive an optimal test suite that can be used for hardware testing in a production line. Our previous study based on applying CIT in cumulative mode; described the systematic application of the strategy for testing 4-bit Magnitude Comparator Integrated Circuits in a ...
We propose a novel strategy to optimize the test suite required for testing both hardware and sof... more We propose a novel strategy to optimize the test suite required for testing both hardware and software in a production line. Here, the strategy is based on two processes: Quality Signing Process and Quality Verification Process, respectively. Unlike earlier work, the proposed strategy is based on integration of black box and white box techniques in order to derive an optimum test suite during the Quality Signing Process. In this case, the generated optimal test suite significantly improves the Quality Verification Process. Considering both processes, the novelty of the proposed strategy is the fact that the optimization and reduction of test suite is performed by selecting only mutant killing test cases from cumulating t-way test cases. As such, the proposed strategy can potentially enhance the quality of product with minimal cost in terms of overall resource usage and time execution. As a case study, this paper describes the step-by-step application of the strategy for testing a 4-bit Magnitude Comparator Integrated Circuits in a production line. Comparatively, our result demonstrates that the proposed strategy outperforms the traditional block partitioning strategy with the mutant score of 100% to 90%, respectively, with the same number of test cases.
2009 IEEE Symposium on Industrial Electronics & Applications, 2009
Abstract Despite being an important activity in the software development cycle (ie to ensure qual... more Abstract Despite being an important activity in the software development cycle (ie to ensure quality and reliability), exhaustive testing is prohibitively impossible. Systematic minimization strategy based on coverage or t-way parameter interactions are often sought for to help minimize the test space. Unlike coverage based minimization strategy which takes a white box approach, t-way parameter interactions based strategy (ie termed t-way testing) takes a black box approach in the sense that no information regarding the implementation is ...
2009 IEEE Symposium on Industrial Electronics & Applications, 2009
Abstract T-way test data generators play an immensely important role for both hardware and softwa... more Abstract T-way test data generators play an immensely important role for both hardware and software configuration testing. Earlier work concludes that t-way test data generator can achieve 100% coverage without having to regard for more than 6 way interactions. In this paper, we investigate whether or not such a conclusion can be applicable for reverse engineering of combinational circuits. In this case, we reverse engineer a faulty commercial eight segment display controller using our t-way test data generator in order to redesign ...
2010 Fourth Asia International Conference on Mathematical/Analytical Modelling and Computer Simulation, 2010
Although desirable as an important activity for quality assurances and enhancing reliability, com... more Although desirable as an important activity for quality assurances and enhancing reliability, complete and exhaustive software testing is prohibitively impossible due to resources as well as timing constraints. While earlier work has indicated that uniform pairwise testing (i.e. based on 2-way interaction of variables) can be effective to detect most faults in a typical software system, a counter argument suggests such conclusion cannot be generalized to all software system faults.
Software testing is an integral part of software engineering. Lack of testing often leads to disa... more Software testing is an integral part of software engineering. Lack of testing often leads to disastrous consequences including loss of data, fortunes, and even lives. In order to ensure software reliability, many combinations of possible input parameters, hardware/software environments, and system configurations need to be tested and verified against for conformance. Due to costing factors as well as time to market constraints, considering all exhaustive test possibilities would be infeasible (i.e. due to combinatorial explosion problem). Earlier work suggests that pairwise sampling strategy (i.e. based on twoway parameter interaction) can be effective. Building and complementing earlier work, this paper discusses an efficient pairwise test data generation strategy, called IRPS. In doing so, IRPS is compared against existing strategies including AETG and its variations, IPO, SA, GA, ACA, and All Pairs. Empirical results demonstrate that IRPS strategy, in most cases, outperformed other strategies as far as the number of test data generated within reasonable time.
ABSTRACT The return routability protocol (RRP) is commonly used in route optimization to secure a... more ABSTRACT The return routability protocol (RRP) is commonly used in route optimization to secure and authenticate mobile IPv6 signals between the mobile node and its correspondent node. In this paper, the correctness and the security of RRP were verified using a Murphi model checker. The results show that RRP has no failure and is correct. However, it is not secure, because an intruder may impersonate a mobile node. Therefore, the design of RRP needs to be revised to overcome these obstacles.
2008 International Symposium on Information Technology, 2008
Generating pairwise test set when the total number of variables is prime numbers has a remarkable... more Generating pairwise test set when the total number of variables is prime numbers has a remarkable property in that the test case generation process can be simplified by applying straightforward strategy that does not require any storage. This paper discusses the said algebraic strategy and compares the results with the well-known orthogonal array strategy. Additionally, this paper also demonstrates the applicability and simplicity of the strategy as compared to orthogonal array to obtain optimal test set for pairwise testing.
2008 First International Conference on Distributed Framework and Applications, 2008
Although desirable as an important activity for ensuring quality assurances and enhancing reliabi... more Although desirable as an important activity for ensuring quality assurances and enhancing reliability, complete and exhaustive software testing is next to impossible due to resources as well as timing constraints. While earlier work has indicated that pairwise testing (i.e. based on 2-way interaction of variables) can be effective to detect most faults in a typical software system, a counter argument suggests such conclusion cannot be generalized to all software system faults. In some system, faults may also be caused by more than two parameters.
2008 International Symposium on Information Technology, 2008
In order to meet market demands for quality software products, software engineers are increasingl... more In order to meet market demands for quality software products, software engineers are increasingly under pressure to test more lines of codes. To maintain acceptable test coverage, software engineers need to consider a significantly large number of test set. Many combinations of possible input parameters, hardware/software environments, and system conditions need to be tested and verified against for conformance. Often, this results into combinatorial explosion problem (i.e. too many test data set too consider). Earlier work suggests that pairwise sampling strategy based on parameter interactions of variables can be effective. This paper discusses an efficient pairwise strategy, termed RA and ORA, that can systematically minimize the pairwise test set generated from higher order test parameters to lower order ones. In doing so, this paper demonstrates and compares the results against existing strategies including IRPS, IPO, GA, ACA, Jenny and All Pairs. Authorized licensed use limited to: UNIVERSITI SAINS MALAYSIA. Downloaded on April 15, 2009 at 05:16 from IEEE Xplore. Restrictions apply.
International Journal of Computer Applications, 2014
Face recognition is a pattern recognition technique and one of the most important biometrics; it ... more Face recognition is a pattern recognition technique and one of the most important biometrics; it is used in a broad spectrum of applications. The accuracy is not a major problem that specifies the performance of automatic face recognition system alone, the time factor is also considered a major factor in real time environments. Recent architecture of the computer system can be employed to solve the time problem, this architecture represented by multi-core CPUs and manycore GPUs that provide the possibility to perform various tasks by parallel processing. However, harnessing the current advancements in computer architecture is not without difficulties. Motivated by such challenge, this paper proposes a Real Time Face Recognition System (RTFRS). In doing so, this paper provides the architectural design, detailed design, and four variant implementations of the RTFRS. Finally, this paper determines the speed up obtained for the three advanced implementations (i.e., Hybrid Parallel model, CPU Parallel model, and Hybrid Mono model) against the convention implementation (i.e., CPU Mono model). The practical results demonstrate that the Hybrid Parallel model gain highest speed up around 82X, CPU Parallel model also have a high speed up around 71X, and finally, the Hybrid Mono model gives a slight speed up about 1.04X.
International Journal of Computer Applications, 2014
ABSTRACT Public key algorithms are extensively known to be slower than symmetric key alternatives... more ABSTRACT Public key algorithms are extensively known to be slower than symmetric key alternatives in the area of cryptographic algorithms for the reason of their basis in modular arithmetic. The most public key algorithm widely used is the RSA. Therefore, how to enhance the speed of RSA algorithm has been the research significant topic in the computer security as well as in computing fields. With remarkable increase in the computing capability of the modern Graphics Processing Unit's (GPUs) as a co-processor of the CPU, one can significantly benefit from the Single Instruction Multiple Thread (SIMT) style of computing. This paper proposes a hybrid system to parallelize the RSA for multicore CPU and many cores GPUs with variable key size. In doing so, three variants implementation for the RSA algorithm are done to facilitate the performance comparison against Crypto++ library and sequential counterpart. The GPU implementation gained approximately 23 speed up factor over the sequential CPU implementation; while the multithread CPU implementation gained only 6 speed up factor over the sequential CPU implementation as far as the latency is concerned. Furthermore, additional speedup could be gained as far as the throughput is concerned; the throughput gained for 1024 bits is ~1800 msg/sec; as for 2048 bits is ~250 msg/sec. Due to overlapping of multithread operation whenever free resources are available. The experiments are conducted on a laptop with Intel Core I7-2670QM, 2. 20 GHz CPU and Nvidia GeForce GT630M GPU. Results reveal that the GPU is appropriate to speed up the RSA algorithm.
Abstract Radio Frequency Identification (RFID) technology; a convenient and flexible technology w... more Abstract Radio Frequency Identification (RFID) technology; a convenient and flexible technology which is well suited for fully automated systems, is directing human lifestyle towards automation and reality. Integrating RFID into attendance management systems makes the tasks of both users and administrators easy, smart, convenient, and practical. Earlier implementations of RFID-based attendance systems involve different approaches and facilities. Different intertwined characteristics (ie, scalability, and automation) are ...
Please cite this article in press as: Ali, M.F.M., et al., Development of Java based RFID applica... more Please cite this article in press as: Ali, M.F.M., et al., Development of Java based RFID application programmable interface for heterogeneous RFID system. a b s t r a c t Developing RFID based applications is a painstakingly difficult endeavor. The difficulties include nonstandard software and hardware peripherals from vendors, interoperability problems between different operating systems as well as lack of expertise in terms of low-level programming for RFID (i.e. steep learning curve). In order to address these difficulties, a reusable RFIDTM API (RFID Tracking & Monitoring Application Programmable Interface) for heterogeneous RFID system has been designed and implemented. The API has been successfully employed in a number of application prototypes including tracking of inventories as well as human/object tracking and tagging. Here, the module has been tested on a number of different types and configuration of active and passive readers including that LF and UHF Readers.
This paper discusses the limitation of both Sequence Covering Array (SCA) and Covering Array (CA)... more This paper discusses the limitation of both Sequence Covering Array (SCA) and Covering Array (CA) for testing reactive system when the order of parameter-values is sensitive. In doing so, this paper proposes a new model to take the sequence values into consideration. Accordingly, by superimposing the CA onto SCA yields another type of combinatorial test suite termed Multi-Valued Sequence Covering Array (MVSCA) in a more generalized form. This superimposing is a challenging process due to NP-Hardness for both SCA and CA. Motivated by such a challenge, this paper presents the MVSCA with a working illustrative example to show the similarities and differences among combinatorial testing methods. Consequently, the MVSCA is a new trend that can be a research vehicle for researchers to develop new and/or modify existing combinatorial strategies to deal with the combinatorial explosion problem raised by the MVSCA.
Software testing is a vital part of the software development life cycle. In many cases, the syste... more Software testing is a vital part of the software development life cycle. In many cases, the system under test has more than one input making the testing efforts for every exhaustive combination impossible (i.e. the time of execution of the test case can be outrageously long). Combinatorial testing offers an alternative to exhaustive testing via considering the interaction of input values for every t-way combination between parameters. Combinatorial testing can be divided into three types which are uniform strength interaction, variable strength interaction and input-output based relation (IOR). IOR combinatorial testing only tests for the important combinations selected by the tester. Most of the researches in combinatorial testing applied the uniform and the variable interaction strength, however, there is still a lack of work addressing IOR. In this paper, a Jaya algorithm is proposed as an optimization algorithm engine to construct a test list based on IOR in the proposed combina...
Online Examination is an essential ingredient in electronic and interactive learning, however, in... more Online Examination is an essential ingredient in electronic and interactive learning, however, in educational environment most of examinations are done in the classical paper-based way due to the lack of resumption capability when power/network/physical computer's component failures. For this reason, adopting and developing an online examination system acts as an active research area in recent years. This paper reviews the state-of-the-art and the-art-of-the-practice for nine general-purpose online examination systems found in the literature, as well as, some dedicated industrial systems based on seven elected intertwined features; namely: secure login, resumption capability, multi-instructor, random question selection, random questions distribution, random choice distribution, and portability implementation method. Even though, the implementation of these systems is promising, however, these systems have some bleeding points. For instance, by practicing the existing examination...
2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA), 2010
Abstract This paper discusses the state of the art of applying combinatorial interaction testing ... more Abstract This paper discusses the state of the art of applying combinatorial interaction testing (CIT) in conjunction with mutation testing for hardware testing. In addition, the paper discusses the art of the practice of applying CIT in normal and cumulative mode in order to derive an optimal test suite that can be used for hardware testing in a production line. Our previous study based on applying CIT in cumulative mode; described the systematic application of the strategy for testing 4-bit Magnitude Comparator Integrated Circuits in a ...
We propose a novel strategy to optimize the test suite required for testing both hardware and sof... more We propose a novel strategy to optimize the test suite required for testing both hardware and software in a production line. Here, the strategy is based on two processes: Quality Signing Process and Quality Verification Process, respectively. Unlike earlier work, the proposed strategy is based on integration of black box and white box techniques in order to derive an optimum test suite during the Quality Signing Process. In this case, the generated optimal test suite significantly improves the Quality Verification Process. Considering both processes, the novelty of the proposed strategy is the fact that the optimization and reduction of test suite is performed by selecting only mutant killing test cases from cumulating t-way test cases. As such, the proposed strategy can potentially enhance the quality of product with minimal cost in terms of overall resource usage and time execution. As a case study, this paper describes the step-by-step application of the strategy for testing a 4-bit Magnitude Comparator Integrated Circuits in a production line. Comparatively, our result demonstrates that the proposed strategy outperforms the traditional block partitioning strategy with the mutant score of 100% to 90%, respectively, with the same number of test cases.
2009 IEEE Symposium on Industrial Electronics & Applications, 2009
Abstract Despite being an important activity in the software development cycle (ie to ensure qual... more Abstract Despite being an important activity in the software development cycle (ie to ensure quality and reliability), exhaustive testing is prohibitively impossible. Systematic minimization strategy based on coverage or t-way parameter interactions are often sought for to help minimize the test space. Unlike coverage based minimization strategy which takes a white box approach, t-way parameter interactions based strategy (ie termed t-way testing) takes a black box approach in the sense that no information regarding the implementation is ...
2009 IEEE Symposium on Industrial Electronics & Applications, 2009
Abstract T-way test data generators play an immensely important role for both hardware and softwa... more Abstract T-way test data generators play an immensely important role for both hardware and software configuration testing. Earlier work concludes that t-way test data generator can achieve 100% coverage without having to regard for more than 6 way interactions. In this paper, we investigate whether or not such a conclusion can be applicable for reverse engineering of combinational circuits. In this case, we reverse engineer a faulty commercial eight segment display controller using our t-way test data generator in order to redesign ...
2010 Fourth Asia International Conference on Mathematical/Analytical Modelling and Computer Simulation, 2010
Although desirable as an important activity for quality assurances and enhancing reliability, com... more Although desirable as an important activity for quality assurances and enhancing reliability, complete and exhaustive software testing is prohibitively impossible due to resources as well as timing constraints. While earlier work has indicated that uniform pairwise testing (i.e. based on 2-way interaction of variables) can be effective to detect most faults in a typical software system, a counter argument suggests such conclusion cannot be generalized to all software system faults.
Software testing is an integral part of software engineering. Lack of testing often leads to disa... more Software testing is an integral part of software engineering. Lack of testing often leads to disastrous consequences including loss of data, fortunes, and even lives. In order to ensure software reliability, many combinations of possible input parameters, hardware/software environments, and system configurations need to be tested and verified against for conformance. Due to costing factors as well as time to market constraints, considering all exhaustive test possibilities would be infeasible (i.e. due to combinatorial explosion problem). Earlier work suggests that pairwise sampling strategy (i.e. based on twoway parameter interaction) can be effective. Building and complementing earlier work, this paper discusses an efficient pairwise test data generation strategy, called IRPS. In doing so, IRPS is compared against existing strategies including AETG and its variations, IPO, SA, GA, ACA, and All Pairs. Empirical results demonstrate that IRPS strategy, in most cases, outperformed other strategies as far as the number of test data generated within reasonable time.
ABSTRACT The return routability protocol (RRP) is commonly used in route optimization to secure a... more ABSTRACT The return routability protocol (RRP) is commonly used in route optimization to secure and authenticate mobile IPv6 signals between the mobile node and its correspondent node. In this paper, the correctness and the security of RRP were verified using a Murphi model checker. The results show that RRP has no failure and is correct. However, it is not secure, because an intruder may impersonate a mobile node. Therefore, the design of RRP needs to be revised to overcome these obstacles.
2008 International Symposium on Information Technology, 2008
Generating pairwise test set when the total number of variables is prime numbers has a remarkable... more Generating pairwise test set when the total number of variables is prime numbers has a remarkable property in that the test case generation process can be simplified by applying straightforward strategy that does not require any storage. This paper discusses the said algebraic strategy and compares the results with the well-known orthogonal array strategy. Additionally, this paper also demonstrates the applicability and simplicity of the strategy as compared to orthogonal array to obtain optimal test set for pairwise testing.
2008 First International Conference on Distributed Framework and Applications, 2008
Although desirable as an important activity for ensuring quality assurances and enhancing reliabi... more Although desirable as an important activity for ensuring quality assurances and enhancing reliability, complete and exhaustive software testing is next to impossible due to resources as well as timing constraints. While earlier work has indicated that pairwise testing (i.e. based on 2-way interaction of variables) can be effective to detect most faults in a typical software system, a counter argument suggests such conclusion cannot be generalized to all software system faults. In some system, faults may also be caused by more than two parameters.
2008 International Symposium on Information Technology, 2008
In order to meet market demands for quality software products, software engineers are increasingl... more In order to meet market demands for quality software products, software engineers are increasingly under pressure to test more lines of codes. To maintain acceptable test coverage, software engineers need to consider a significantly large number of test set. Many combinations of possible input parameters, hardware/software environments, and system conditions need to be tested and verified against for conformance. Often, this results into combinatorial explosion problem (i.e. too many test data set too consider). Earlier work suggests that pairwise sampling strategy based on parameter interactions of variables can be effective. This paper discusses an efficient pairwise strategy, termed RA and ORA, that can systematically minimize the pairwise test set generated from higher order test parameters to lower order ones. In doing so, this paper demonstrates and compares the results against existing strategies including IRPS, IPO, GA, ACA, Jenny and All Pairs. Authorized licensed use limited to: UNIVERSITI SAINS MALAYSIA. Downloaded on April 15, 2009 at 05:16 from IEEE Xplore. Restrictions apply.
International Journal of Computer Applications, 2014
Face recognition is a pattern recognition technique and one of the most important biometrics; it ... more Face recognition is a pattern recognition technique and one of the most important biometrics; it is used in a broad spectrum of applications. The accuracy is not a major problem that specifies the performance of automatic face recognition system alone, the time factor is also considered a major factor in real time environments. Recent architecture of the computer system can be employed to solve the time problem, this architecture represented by multi-core CPUs and manycore GPUs that provide the possibility to perform various tasks by parallel processing. However, harnessing the current advancements in computer architecture is not without difficulties. Motivated by such challenge, this paper proposes a Real Time Face Recognition System (RTFRS). In doing so, this paper provides the architectural design, detailed design, and four variant implementations of the RTFRS. Finally, this paper determines the speed up obtained for the three advanced implementations (i.e., Hybrid Parallel model, CPU Parallel model, and Hybrid Mono model) against the convention implementation (i.e., CPU Mono model). The practical results demonstrate that the Hybrid Parallel model gain highest speed up around 82X, CPU Parallel model also have a high speed up around 71X, and finally, the Hybrid Mono model gives a slight speed up about 1.04X.
International Journal of Computer Applications, 2014
ABSTRACT Public key algorithms are extensively known to be slower than symmetric key alternatives... more ABSTRACT Public key algorithms are extensively known to be slower than symmetric key alternatives in the area of cryptographic algorithms for the reason of their basis in modular arithmetic. The most public key algorithm widely used is the RSA. Therefore, how to enhance the speed of RSA algorithm has been the research significant topic in the computer security as well as in computing fields. With remarkable increase in the computing capability of the modern Graphics Processing Unit's (GPUs) as a co-processor of the CPU, one can significantly benefit from the Single Instruction Multiple Thread (SIMT) style of computing. This paper proposes a hybrid system to parallelize the RSA for multicore CPU and many cores GPUs with variable key size. In doing so, three variants implementation for the RSA algorithm are done to facilitate the performance comparison against Crypto++ library and sequential counterpart. The GPU implementation gained approximately 23 speed up factor over the sequential CPU implementation; while the multithread CPU implementation gained only 6 speed up factor over the sequential CPU implementation as far as the latency is concerned. Furthermore, additional speedup could be gained as far as the throughput is concerned; the throughput gained for 1024 bits is ~1800 msg/sec; as for 2048 bits is ~250 msg/sec. Due to overlapping of multithread operation whenever free resources are available. The experiments are conducted on a laptop with Intel Core I7-2670QM, 2. 20 GHz CPU and Nvidia GeForce GT630M GPU. Results reveal that the GPU is appropriate to speed up the RSA algorithm.
Abstract Radio Frequency Identification (RFID) technology; a convenient and flexible technology w... more Abstract Radio Frequency Identification (RFID) technology; a convenient and flexible technology which is well suited for fully automated systems, is directing human lifestyle towards automation and reality. Integrating RFID into attendance management systems makes the tasks of both users and administrators easy, smart, convenient, and practical. Earlier implementations of RFID-based attendance systems involve different approaches and facilities. Different intertwined characteristics (ie, scalability, and automation) are ...
Please cite this article in press as: Ali, M.F.M., et al., Development of Java based RFID applica... more Please cite this article in press as: Ali, M.F.M., et al., Development of Java based RFID application programmable interface for heterogeneous RFID system. a b s t r a c t Developing RFID based applications is a painstakingly difficult endeavor. The difficulties include nonstandard software and hardware peripherals from vendors, interoperability problems between different operating systems as well as lack of expertise in terms of low-level programming for RFID (i.e. steep learning curve). In order to address these difficulties, a reusable RFIDTM API (RFID Tracking & Monitoring Application Programmable Interface) for heterogeneous RFID system has been designed and implemented. The API has been successfully employed in a number of application prototypes including tracking of inventories as well as human/object tracking and tagging. Here, the module has been tested on a number of different types and configuration of active and passive readers including that LF and UHF Readers.
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