In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Arou... more In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Around (GAA) long-channel junctionless MOSFET model in Verilog-A code, which will be further used in commercial circuit simulators. The model in Verilog-A is integrated in the SmartSpice circuit simulator and tested in a CMOS inverter. Both p-channel and n-channel device models are validated. Also, the results are compared with data from 3D numerical simulations, showing a very good agreement in all transistors' operation regimes.
Since the invention of the integrated circuit (IC) in 1958, engineers and researchers around the ... more Since the invention of the integrated circuit (IC) in 1958, engineers and researchers around the world have worked on how to put more speed, performance and value onto smaller chips of silicon. The semiconductor industry has made considerable progress, especially regarding the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The fundamental driver has been the continued shrinking of its feature sizes, allowing the exponential growth in device count that tracks the well-known Moore's Law, first formulated by Intel co-founder Gordon Moore. However, this law is a rough prediction of the future of IC expansion. The need of a more accurate forecast defined the International Technology Roadmap for Semiconductors (ITRS), which has been predicting and driving the pace of semiconductor technology at the same time. The use of CMOS technology also for high-frequency (HF) applications is now common. This is due to the significant increase in the unity current gain frequency of modern deep submicrometer MOS devices. However, to be competitive against other technologies for high-frequency (HF) applications, MOSFETs need to demonstrate comparable noise performance. Although the channel thermal noise of MOSFET has been known to be the most dominant source of noise in the device, additional noise sources emerge as the CMOS technology scales down, such as gate tunneling current, and substrate noise. On the other hand, since the noise figure of the MOSFET decreases with technology scaling, HF noise measurement, and characterization of extremely small devices is becoming more challenging. Due to these challenges, there is a lot of research around new technologies, new materials and new devices. This chapter presents a review of some of the recent results in this exciting area.
Facta universitatis - series: Electronics and Energetics, 2018
Amorphous In-Ga-Zn-O Thin Film Transistors (a-IGZO TFTs) have proven to be an excellent approach ... more Amorphous In-Ga-Zn-O Thin Film Transistors (a-IGZO TFTs) have proven to be an excellent approach for flat panel display drivers using organic light emitting diodes, due to their high mobility and stability compared to other types of TFTs. These characteristics are related to the specifics of the metal-oxygen-metal bonds, which give raise to spatially distributed s orbitals that can overlap between them. The magnitude of the overlap between s orbitals seems to be little sensitive to the presence of the distorted bonds, allowing high values of mobility, even in devices fabricated at room temperature. In this paper, we show the effect of the distribution of states in the a-IGZO layer on the main conduction mechanism of the a-IGZO TFTs, analyzing the behavior with temperature of the drain current.
We present a new complete capacitance model for the amorphous indium-gallium-zinc-oxide (IGZO) th... more We present a new complete capacitance model for the amorphous indium-gallium-zinc-oxide (IGZO) thin-film-transistor (TFT), valid in the above-threshold and subthreshold regime (Fermi level in the tail and deep states, respectively). The parameters applied in the model are analytically extracted from the current–voltage characteristics of the devices, using a previously developed unified model and parameter extraction method. The good agreement between our capacitance model and 3D numerical TCAD simulations proves the validity of this letter, which is expected to be useful for the optimization of fabrication processes and for the prospective estimation of the effect of process conditions on circuit performances.
The accuracy and continuity of the C- V characteristics of a transistor at Vds = 0 is one of the ... more The accuracy and continuity of the C- V characteristics of a transistor at Vds = 0 is one of the main benchmark tests a good compact model must pass. Singularities (in the form of 0/0 divisions) at Vds = 0 in compact capacitance models developed for several types of undoped 3-terminal devices, such as Double-Gate and Surrounding-Gate MOSFETs, have been corrected by means of techniques based on dealing individually with each of the targeted devices. Due to the lengthy calculations required for each of those particular cases, it will be useful to develop relationships between capacitances, with expressions easy to calculate, that can be applied to any type of undoped 3-terminal FET. We present compact modeling schemes valid for long-channel 3-terminal devices at Vds = 0 and we demonstrate suitable relationships between the different capacitances, deriving general analytic expressions for them in terms of the derivative of the drain charge sheet density with respect to the drain voltage; we also show how they can be calculated using the device charge control model.
This paper presents a new approach for an analytical model of nanoscale double-gate (DG) MOSFET. ... more This paper presents a new approach for an analytical model of nanoscale double-gate (DG) MOSFET. The equivalent circuit is considered over a fully distributed active line, opening the door to obtain a compact and unified small equivalent circuit that includes noise contributions.
2012 13th International Conference on Ultimate Integration on Silicon (ULIS), 2012
We present a compact physics-based model of the current-voltage characteristics of graphene field... more We present a compact physics-based model of the current-voltage characteristics of graphene field-effect transistors, of especial interest for analog and radio-frequency applications where bandgap engineering of graphene could be not needed. The physical framework is a field-effect model and drift-diffusion carrier transport. Explicit closed-form expressions have been derived for the drain current covering continuosly all operation regions. The model has been benchmarked with measured prototype devices, demonstrating accuracy and predictive behavior.
ABSTRACT In this paper we present a simple compact model for the computation of the drain current... more ABSTRACT In this paper we present a simple compact model for the computation of the drain current in a new type of transistor, a junctionless VBT (Variable Barrier Transistor).A good agreement between our results and two TCAD simulation tools (COMSOL and ATLAS), proves the accuracy of this model. It is the first time that a compact drain current model is derived for this type of transistor.
ABSTRACT In this paper, we solved Poisson equation in cylindrical coordinates using approximation... more ABSTRACT In this paper, we solved Poisson equation in cylindrical coordinates using approximations to obtain a compact model for the drain current of long-channel junctionless gate-all-around MOSFETs. The resulting model is analytical, explicit, and valid for depletion and accumulation, and consists of simple physically based equations, for better understanding of this device, and also easier implementation and better computation speed as a compact model. The agreement with TCAD simulations is very good.
Proceedings of the 8th Spanish Conference on Electron Devices, CDE'2011, 2011
In this work we present a simple model for computing the current-voltage characteristics of graph... more In this work we present a simple model for computing the current-voltage characteristics of graphene based transistors (G-FETs). Our model is based on a simple treatment of electrostatics and a transport module including both tunneling and thermionic currents, properly capturing the effect of physical and electrical parameters. The predictive behaviour is demonstrated via comparison with experimental measurements of devices.
ABSTRACT The accuracy and continuity of the C–V characteristics of a transistor at Vds=0 is one o... more ABSTRACT The accuracy and continuity of the C–V characteristics of a transistor at Vds=0 is one of the main benchmark tests a good compact model must pass. Singularities (in the form of 0/0 divisions) at Vds=0 in compact capacitance models developed for several types of undoped 3-terminal devices, such as Double-Gate and Surrounding-Gate MOSFETs, have been corrected by means of techniques based on dealing individually with each of the targeted devices. Due to the lengthy calculations required for each of those particular cases, it will be useful to develop relationships between capacitances, with expressions easy to calculate, that can be applied to any type of undoped 3-terminal FET. We present compact modeling schemes valid for long-channel 3-terminal devices at Vds=0 and we demonstrate suitable relationships between the different capacitances, deriving general analytic expressions for them in terms of the derivative of the drain charge sheet density with respect to the drain voltage; we also show how they can be calculated using the device charge control model.
In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Arou... more In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Around (GAA) long-channel junctionless MOSFET model in Verilog-A code, which will be further used in commercial circuit simulators. The model in Verilog-A is integrated in the SmartSpice circuit simulator and tested in a CMOS inverter. Both p-channel and n-channel device models are validated. Also, the results are compared with data from 3D numerical simulations, showing a very good agreement in all transistors' operation regimes.
Since the invention of the integrated circuit (IC) in 1958, engineers and researchers around the ... more Since the invention of the integrated circuit (IC) in 1958, engineers and researchers around the world have worked on how to put more speed, performance and value onto smaller chips of silicon. The semiconductor industry has made considerable progress, especially regarding the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The fundamental driver has been the continued shrinking of its feature sizes, allowing the exponential growth in device count that tracks the well-known Moore's Law, first formulated by Intel co-founder Gordon Moore. However, this law is a rough prediction of the future of IC expansion. The need of a more accurate forecast defined the International Technology Roadmap for Semiconductors (ITRS), which has been predicting and driving the pace of semiconductor technology at the same time. The use of CMOS technology also for high-frequency (HF) applications is now common. This is due to the significant increase in the unity current gain frequency of modern deep submicrometer MOS devices. However, to be competitive against other technologies for high-frequency (HF) applications, MOSFETs need to demonstrate comparable noise performance. Although the channel thermal noise of MOSFET has been known to be the most dominant source of noise in the device, additional noise sources emerge as the CMOS technology scales down, such as gate tunneling current, and substrate noise. On the other hand, since the noise figure of the MOSFET decreases with technology scaling, HF noise measurement, and characterization of extremely small devices is becoming more challenging. Due to these challenges, there is a lot of research around new technologies, new materials and new devices. This chapter presents a review of some of the recent results in this exciting area.
Facta universitatis - series: Electronics and Energetics, 2018
Amorphous In-Ga-Zn-O Thin Film Transistors (a-IGZO TFTs) have proven to be an excellent approach ... more Amorphous In-Ga-Zn-O Thin Film Transistors (a-IGZO TFTs) have proven to be an excellent approach for flat panel display drivers using organic light emitting diodes, due to their high mobility and stability compared to other types of TFTs. These characteristics are related to the specifics of the metal-oxygen-metal bonds, which give raise to spatially distributed s orbitals that can overlap between them. The magnitude of the overlap between s orbitals seems to be little sensitive to the presence of the distorted bonds, allowing high values of mobility, even in devices fabricated at room temperature. In this paper, we show the effect of the distribution of states in the a-IGZO layer on the main conduction mechanism of the a-IGZO TFTs, analyzing the behavior with temperature of the drain current.
We present a new complete capacitance model for the amorphous indium-gallium-zinc-oxide (IGZO) th... more We present a new complete capacitance model for the amorphous indium-gallium-zinc-oxide (IGZO) thin-film-transistor (TFT), valid in the above-threshold and subthreshold regime (Fermi level in the tail and deep states, respectively). The parameters applied in the model are analytically extracted from the current–voltage characteristics of the devices, using a previously developed unified model and parameter extraction method. The good agreement between our capacitance model and 3D numerical TCAD simulations proves the validity of this letter, which is expected to be useful for the optimization of fabrication processes and for the prospective estimation of the effect of process conditions on circuit performances.
The accuracy and continuity of the C- V characteristics of a transistor at Vds = 0 is one of the ... more The accuracy and continuity of the C- V characteristics of a transistor at Vds = 0 is one of the main benchmark tests a good compact model must pass. Singularities (in the form of 0/0 divisions) at Vds = 0 in compact capacitance models developed for several types of undoped 3-terminal devices, such as Double-Gate and Surrounding-Gate MOSFETs, have been corrected by means of techniques based on dealing individually with each of the targeted devices. Due to the lengthy calculations required for each of those particular cases, it will be useful to develop relationships between capacitances, with expressions easy to calculate, that can be applied to any type of undoped 3-terminal FET. We present compact modeling schemes valid for long-channel 3-terminal devices at Vds = 0 and we demonstrate suitable relationships between the different capacitances, deriving general analytic expressions for them in terms of the derivative of the drain charge sheet density with respect to the drain voltage; we also show how they can be calculated using the device charge control model.
This paper presents a new approach for an analytical model of nanoscale double-gate (DG) MOSFET. ... more This paper presents a new approach for an analytical model of nanoscale double-gate (DG) MOSFET. The equivalent circuit is considered over a fully distributed active line, opening the door to obtain a compact and unified small equivalent circuit that includes noise contributions.
2012 13th International Conference on Ultimate Integration on Silicon (ULIS), 2012
We present a compact physics-based model of the current-voltage characteristics of graphene field... more We present a compact physics-based model of the current-voltage characteristics of graphene field-effect transistors, of especial interest for analog and radio-frequency applications where bandgap engineering of graphene could be not needed. The physical framework is a field-effect model and drift-diffusion carrier transport. Explicit closed-form expressions have been derived for the drain current covering continuosly all operation regions. The model has been benchmarked with measured prototype devices, demonstrating accuracy and predictive behavior.
ABSTRACT In this paper we present a simple compact model for the computation of the drain current... more ABSTRACT In this paper we present a simple compact model for the computation of the drain current in a new type of transistor, a junctionless VBT (Variable Barrier Transistor).A good agreement between our results and two TCAD simulation tools (COMSOL and ATLAS), proves the accuracy of this model. It is the first time that a compact drain current model is derived for this type of transistor.
ABSTRACT In this paper, we solved Poisson equation in cylindrical coordinates using approximation... more ABSTRACT In this paper, we solved Poisson equation in cylindrical coordinates using approximations to obtain a compact model for the drain current of long-channel junctionless gate-all-around MOSFETs. The resulting model is analytical, explicit, and valid for depletion and accumulation, and consists of simple physically based equations, for better understanding of this device, and also easier implementation and better computation speed as a compact model. The agreement with TCAD simulations is very good.
Proceedings of the 8th Spanish Conference on Electron Devices, CDE'2011, 2011
In this work we present a simple model for computing the current-voltage characteristics of graph... more In this work we present a simple model for computing the current-voltage characteristics of graphene based transistors (G-FETs). Our model is based on a simple treatment of electrostatics and a transport module including both tunneling and thermionic currents, properly capturing the effect of physical and electrical parameters. The predictive behaviour is demonstrated via comparison with experimental measurements of devices.
ABSTRACT The accuracy and continuity of the C–V characteristics of a transistor at Vds=0 is one o... more ABSTRACT The accuracy and continuity of the C–V characteristics of a transistor at Vds=0 is one of the main benchmark tests a good compact model must pass. Singularities (in the form of 0/0 divisions) at Vds=0 in compact capacitance models developed for several types of undoped 3-terminal devices, such as Double-Gate and Surrounding-Gate MOSFETs, have been corrected by means of techniques based on dealing individually with each of the targeted devices. Due to the lengthy calculations required for each of those particular cases, it will be useful to develop relationships between capacitances, with expressions easy to calculate, that can be applied to any type of undoped 3-terminal FET. We present compact modeling schemes valid for long-channel 3-terminal devices at Vds=0 and we demonstrate suitable relationships between the different capacitances, deriving general analytic expressions for them in terms of the derivative of the drain charge sheet density with respect to the drain voltage; we also show how they can be calculated using the device charge control model.
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