In this paper a methodology for architectural level power optimization of a superscalar processor is proposed. The optimization is targeted at high performance real-time DSP operations. Sample Rate Conversion operation in Software Defined... more
In this paper a methodology for architectural level power optimization of a superscalar processor is proposed. The optimization is targeted at high performance real-time DSP operations. Sample Rate Conversion operation in Software Defined Radios has been taken as an exemplar ...
