ABSTRACT This work presented an experimental analysis of the nonlinearity of p- and n-type JNTs (... more ABSTRACT This work presented an experimental analysis of the nonlinearity of p- and n-type JNTs (junctionless nanowire transistors) of several L. It is shown that, at a fixed input bias VA, HD2 degrades with the raise of L due to lower the effect of RS and at a targeted V0, HD2 improves with L increase owing to the larger AV resulting from the smaller channel length modulation.
ABSTRACT This work presents an experimental analysis of the low-frequency noise and the effective... more ABSTRACT This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained–rotated SOI n-type FinFETs, respectively, for several fin widths biased at different gate voltages. Additionally, the profile of the effective trap density is presented along the depth of the gate dielectric of the devices. It is shown that strained devices present higher noise than conventional ones, independent on the fin width, which can be explained by poorer interface quality observed in strained devices. On the other hand, the low frequency noise of narrow rotated devices, where the main conduction path changes from top to sidewalls, has shown to reduce as the interface integrity is improved by substrate rotation. All the evaluated devices presented 1/f noise as the dominant noise component up to 1 kHz.
ABSTRACT This work presented an experimental study of the influence of combining the biaxial stra... more ABSTRACT This work presented an experimental study of the influence of combining the biaxial strain and 45° substrate rotation on the low-frequency noise of triple gate MuGFETs with different WFin and bias conditions. The results showed a 1/f noise characteristic for the strained and strained rotated devices in linear region, independent of WFin The strained rotated nMuGFET presents a lower LFN for narrow dimensions for practically all VGT condition, meanwhile for wider devices the opposite was found. The substrate rotation of strained MuGFETs is able to reduce the sidewall LFN.
ABSTRACT In this work the influence of the substrate rotation on the analog performance of strain... more ABSTRACT In this work the influence of the substrate rotation on the analog performance of strained SOI MuGFETs is presented. Measurements performed in fabricated devices show a degradation of the maximum transconductance at both linear and saturation regime. The substrate rotation has no influence on the output conductance. The intrinsic voltage gain and the unit gain frequency were extracted and presented a reduction promoted by substrate rotation, being more evident for a narrow fin.
2010 IEEE International SOI Conference (SOI), 2010
... [5] where the absence of ZTC in JL devices is discussed. The maximum transconductance of JL d... more ... [5] where the absence of ZTC in JL devices is discussed. The maximum transconductance of JL devices as a function of T at VDS = 50 mV for experimental results is presented in Fig. ... Symbols gm,max @ VDS=50 mV g m [ S] ...
2012 IEEE International SOI Conference (SOI), 2012
ABSTRACT This work presented an experimental analysis of the LFN in p and n-type JNTs of differen... more ABSTRACT This work presented an experimental analysis of the LFN in p and n-type JNTs of different L and doping concentrations. JNTs have shown 1/f noise as the main noise component, which has been associated to CNF in nMOS and MF in the pMOS. Also, SId reduced with the rise of the doping concentration and with the raise of L.
2012 IEEE International SOI Conference (SOI), 2012
ABSTRACT This work presented an evaluation of the zero temperature coefficient bias in Junctionle... more ABSTRACT This work presented an evaluation of the zero temperature coefficient bias in Junctionless Nanowire Transistors. Contrarily to results of previous works, this paper shows that JNTs can present a ZTC point, which depends on the series resistance and its dependence on the temperature.
28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), 2013
ABSTRACT This paper aims to analyze the charges density in multiple gates junctionless devices wi... more ABSTRACT This paper aims to analyze the charges density in multiple gates junctionless devices with different dimensions.. The analysis of the charge densities was done at the center of the silicon film, at the sidewall and at the top interfaces between the silicon and the gate oxide, for devices with different fin width, height and gate oxide tickness. Based on this analisys, the occurrence of corner effects in Junctionless devices is investigated.
ABSTRACT A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless ... more ABSTRACT A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 1019 cm−3, as well as for layer thicknesses of 10, 15 and 20 nm. The model is physically-based, considering both the depletion and accumulation operating conditions. Most model parameters are related to physical magnitudes, and the extraction procedure for each of them is well established. The model provides an accurate description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of the requirement of being symmetrical with respect to Vd = 0 V.
ABSTRACT In this work an analysis of junctionless nanowire nMOS transistors for the implementatio... more ABSTRACT In this work an analysis of junctionless nanowire nMOS transistors for the implementation of quasi-linear resistor is presented. The study is based on experimental results of fabricated devices operating in a large range of temperatures, between 300 K and 573 K. The parasitic series resistance plays an important role in the harmonic distortion characteristics, reducing the nonlinearity of JNTs acting as quasi-linear resistor.
ABSTRACT The effect of the source/drain parasitic resistance (R S) on the I-V characteristics of ... more ABSTRACT The effect of the source/drain parasitic resistance (R S) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on R S has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.
ABSTRACT This work proposes a physically-based analytical model for the non-linearity of Triple-G... more ABSTRACT This work proposes a physically-based analytical model for the non-linearity of Triple-Gate MOSFETs. The model describes the second order harmonic distortion (HD2), usually the major non-linearity source, as a function of the device dimensions, the series resistance, the low field mobility and the mobility degradation factor (theta). The model was applied to transistors of different channel lengths and fin widths and allowed to conclude that theta is the parameter which most contributes for the increase of HD2. The model was validated for both unstrained and strained FinFETs.
Harmonic Distortion Analysis of SOI Triple Gate FinFETs Applied to 2-MOS Balanced Structures. [EC... more Harmonic Distortion Analysis of SOI Triple Gate FinFETs Applied to 2-MOS Balanced Structures. [ECS Transactions 19, 289 (2009)]. Rodrigo T. Doria, Joao A. Martino, Antonio Cerdeira, Marcelo Pavanello. Abstract. This work ...
Abstract This paper examines the linearity of 2-MOS MOSFET-C balanced structures using convention... more Abstract This paper examines the linearity of 2-MOS MOSFET-C balanced structures using conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices. The distortion analysis has been performed through the evaluation of third order harmonic distortion (HD3). The study has been carried out through experimental results, two-dimensional process and device simulations. Along this work, the best operation bias in terms of HD3 is determined for each analysed device and the couple device that exhibits lower HD3 is ...
Abstract This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around ... more Abstract This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures ...
28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), 2013
ABSTRACT The linearity of junctionless nanowire transistors operating in the linear regime has be... more ABSTRACT The linearity of junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature and the series resistance on the overall linearity have been evaluated. It is demonstrated that the increase of the series resistance improves the second order distortion and degrades the third order one.
ABSTRACT This work presented an experimental analysis of the nonlinearity of p- and n-type JNTs (... more ABSTRACT This work presented an experimental analysis of the nonlinearity of p- and n-type JNTs (junctionless nanowire transistors) of several L. It is shown that, at a fixed input bias VA, HD2 degrades with the raise of L due to lower the effect of RS and at a targeted V0, HD2 improves with L increase owing to the larger AV resulting from the smaller channel length modulation.
ABSTRACT This work presents an experimental analysis of the low-frequency noise and the effective... more ABSTRACT This work presents an experimental analysis of the low-frequency noise and the effective trap density of conventional, strained, rotated and strained–rotated SOI n-type FinFETs, respectively, for several fin widths biased at different gate voltages. Additionally, the profile of the effective trap density is presented along the depth of the gate dielectric of the devices. It is shown that strained devices present higher noise than conventional ones, independent on the fin width, which can be explained by poorer interface quality observed in strained devices. On the other hand, the low frequency noise of narrow rotated devices, where the main conduction path changes from top to sidewalls, has shown to reduce as the interface integrity is improved by substrate rotation. All the evaluated devices presented 1/f noise as the dominant noise component up to 1 kHz.
ABSTRACT This work presented an experimental study of the influence of combining the biaxial stra... more ABSTRACT This work presented an experimental study of the influence of combining the biaxial strain and 45° substrate rotation on the low-frequency noise of triple gate MuGFETs with different WFin and bias conditions. The results showed a 1/f noise characteristic for the strained and strained rotated devices in linear region, independent of WFin The strained rotated nMuGFET presents a lower LFN for narrow dimensions for practically all VGT condition, meanwhile for wider devices the opposite was found. The substrate rotation of strained MuGFETs is able to reduce the sidewall LFN.
ABSTRACT In this work the influence of the substrate rotation on the analog performance of strain... more ABSTRACT In this work the influence of the substrate rotation on the analog performance of strained SOI MuGFETs is presented. Measurements performed in fabricated devices show a degradation of the maximum transconductance at both linear and saturation regime. The substrate rotation has no influence on the output conductance. The intrinsic voltage gain and the unit gain frequency were extracted and presented a reduction promoted by substrate rotation, being more evident for a narrow fin.
2010 IEEE International SOI Conference (SOI), 2010
... [5] where the absence of ZTC in JL devices is discussed. The maximum transconductance of JL d... more ... [5] where the absence of ZTC in JL devices is discussed. The maximum transconductance of JL devices as a function of T at VDS = 50 mV for experimental results is presented in Fig. ... Symbols gm,max @ VDS=50 mV g m [ S] ...
2012 IEEE International SOI Conference (SOI), 2012
ABSTRACT This work presented an experimental analysis of the LFN in p and n-type JNTs of differen... more ABSTRACT This work presented an experimental analysis of the LFN in p and n-type JNTs of different L and doping concentrations. JNTs have shown 1/f noise as the main noise component, which has been associated to CNF in nMOS and MF in the pMOS. Also, SId reduced with the rise of the doping concentration and with the raise of L.
2012 IEEE International SOI Conference (SOI), 2012
ABSTRACT This work presented an evaluation of the zero temperature coefficient bias in Junctionle... more ABSTRACT This work presented an evaluation of the zero temperature coefficient bias in Junctionless Nanowire Transistors. Contrarily to results of previous works, this paper shows that JNTs can present a ZTC point, which depends on the series resistance and its dependence on the temperature.
28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), 2013
ABSTRACT This paper aims to analyze the charges density in multiple gates junctionless devices wi... more ABSTRACT This paper aims to analyze the charges density in multiple gates junctionless devices with different dimensions.. The analysis of the charge densities was done at the center of the silicon film, at the sidewall and at the top interfaces between the silicon and the gate oxide, for devices with different fin width, height and gate oxide tickness. Based on this analisys, the occurrence of corner effects in Junctionless devices is investigated.
ABSTRACT A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless ... more ABSTRACT A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 1019 cm−3, as well as for layer thicknesses of 10, 15 and 20 nm. The model is physically-based, considering both the depletion and accumulation operating conditions. Most model parameters are related to physical magnitudes, and the extraction procedure for each of them is well established. The model provides an accurate description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of the requirement of being symmetrical with respect to Vd = 0 V.
ABSTRACT In this work an analysis of junctionless nanowire nMOS transistors for the implementatio... more ABSTRACT In this work an analysis of junctionless nanowire nMOS transistors for the implementation of quasi-linear resistor is presented. The study is based on experimental results of fabricated devices operating in a large range of temperatures, between 300 K and 573 K. The parasitic series resistance plays an important role in the harmonic distortion characteristics, reducing the nonlinearity of JNTs acting as quasi-linear resistor.
ABSTRACT The effect of the source/drain parasitic resistance (R S) on the I-V characteristics of ... more ABSTRACT The effect of the source/drain parasitic resistance (R S) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on R S has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on R S is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.
ABSTRACT This work proposes a physically-based analytical model for the non-linearity of Triple-G... more ABSTRACT This work proposes a physically-based analytical model for the non-linearity of Triple-Gate MOSFETs. The model describes the second order harmonic distortion (HD2), usually the major non-linearity source, as a function of the device dimensions, the series resistance, the low field mobility and the mobility degradation factor (theta). The model was applied to transistors of different channel lengths and fin widths and allowed to conclude that theta is the parameter which most contributes for the increase of HD2. The model was validated for both unstrained and strained FinFETs.
Harmonic Distortion Analysis of SOI Triple Gate FinFETs Applied to 2-MOS Balanced Structures. [EC... more Harmonic Distortion Analysis of SOI Triple Gate FinFETs Applied to 2-MOS Balanced Structures. [ECS Transactions 19, 289 (2009)]. Rodrigo T. Doria, Joao A. Martino, Antonio Cerdeira, Marcelo Pavanello. Abstract. This work ...
Abstract This paper examines the linearity of 2-MOS MOSFET-C balanced structures using convention... more Abstract This paper examines the linearity of 2-MOS MOSFET-C balanced structures using conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices. The distortion analysis has been performed through the evaluation of third order harmonic distortion (HD3). The study has been carried out through experimental results, two-dimensional process and device simulations. Along this work, the best operation bias in terms of HD3 is determined for each analysed device and the couple device that exhibits lower HD3 is ...
Abstract This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around ... more Abstract This work studies the linearity of conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices when applied in 2-MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures ...
28th Symposium on Microelectronics Technology and Devices (SBMicro 2013), 2013
ABSTRACT The linearity of junctionless nanowire transistors operating in the linear regime has be... more ABSTRACT The linearity of junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature and the series resistance on the overall linearity have been evaluated. It is demonstrated that the increase of the series resistance improves the second order distortion and degrades the third order one.
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