The paper covers a simple RTL implementation of a command processor with its associated macroinst... more The paper covers a simple RTL implementation of a command processor with its associated macroinstructions implemented on FPGA device to drive an external peripherals having processor like bus interface. Soft processor is used inside FPGA device to handle the tasks of software driver for peripheral controller. The paper discusses an approach to mimic a simple soft processor to handle the task at core layer of driver for basic communication with peripherals connected to FPGA. The present architecture envisages a three-tier implementation of peripheral hardware software co-design interface. The Top level is an application processor connected to FPGA for handling high-level application layers. The application processor could be a generic processor or a DSP. The next second level is a soft processor embedded in FPGA for handling middle layer software. Command processor or pre-processor handles the third bottom core layer task/command specific processing
—Adaptive Digital filter based on Least Mean Square (LMS) algorithm is widely used in the field o... more —Adaptive Digital filter based on Least Mean Square (LMS) algorithm is widely used in the field of Digital Signal processing to iteratively estimate the statistics of an unknown signal. Architecture of adaptive filter is based on three major computing elements namely multiplier, adder and delay unit to realize the Finite Impulse Response (FIR) filter. The coefficients of the FIR filter are adjusted automatically by LMS of the error so as to match the adapted output to the desired input. This paper explains the design of adaptive filter by two approaches. One is model based approach and other is Field Programmable Gate Arrays (FPGAs). The model based design approach is developed around MATLAB, SIMULINK and SYSTEM GENERATOR tools, which provide a virtual FPGA platform. Modern FPGA include the resources needed to design efficient filtering structures. The LMS algorithm has been implemented on CYCLONE II EP2C35F672C8 FPGA device, using ALTERA QUARTUS II development platform. The three major demonstrable applications cited in the present work are System Identification, Noise reduction and Echo cancellation.
System on programmable chip for the performance estimation of loom machine, which calculates the ... more System on programmable chip for the performance estimation of loom machine, which calculates the efficiency and meter count for weaved cloth automatically. Also it calculates the efficiency of loom machine. Previously the same was done using manual process which was not efficient. This article is intended for loom machines which are not modern.
2010 International Conference on Computer Applications and Industrial Electronics, 2010
... For Computation Intensive Applications on FPGA Sheetal Bhandari, Shashank Pujari,Avinash Inte... more ... For Computation Intensive Applications on FPGA Sheetal Bhandari, Shashank Pujari,Avinash International Institute of Information Technology Pune, India E-mail: (sheetalb, shashankp)@isquareit.ac.in, avinash_nov09@vlsi.isquareit.ac.in ...
Embedded Computing platforms based on
Microcontroller, Field Programmable Gate Array (FPGA) and
... more Embedded Computing platforms based on Microcontroller, Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) are subjects of interest at Under Graduate(UG) and Post Graduate(PG) levels in Electronics and Communication Engineering. Real Time Signal Processing algorithms are generally implemented on any one of these platforms. The paper presents a comparative performance analysis between Microcontroller and FPGA based signal processing by way of a case study on Finite Impulse Response (FIR) fIlter implementation. Microcontrollers are basically sequential and FPGAs are parallel computing platforms. This paper highlights the parallelism feature of FPGA to prove its efficiency against Microcontroller for signal processing applications.
With increased resource size, powerful DSP
blocks and large on-chip memory, Field Programmable Ga... more With increased resource size, powerful DSP blocks and large on-chip memory, Field Programmable Gate Array (FPGA) devices play a major role as hardware platforms for implementing compute intensive video image processing applications. In this paper, image processing algorithms are used for tracking a moving video object. The image processing algorithms used are (a) Noisy video generation with random motion (b) Video image median filter (c) Video image back ground removal (d) Video image thresholding (e) Video image edge detection (f) Video image height and width calculation (g) Video image center computation (h) Video image and center image overlay. The image processing algorithms are developed initially by Model Based Design Approach using Simulink models of MATHWORK’s MATLAB Tool. Then these algorithms are implemented on ALTERA CYCLONE-II FPGA device using TERASIC DE2 FPGA hardware kit and ALTERA QUARTUS-II software tool. The input video image is taken from a NTSC/PAL camera and processed in real time using the algorithms on the FPGA and the resulted tracked video image output is displayed on a VGA monitor.
Abstract— Filtering data in real-time requires dedicated
hardware to meet demanding time requirem... more Abstract— Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signals are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. Modern field programmable gate arrays (FPGAs) include the resources needed to design efficient filtering structures. The present work deals with the design and implementation of FPGA based adaptive filter for echo cancellation. Here LMS algorithm, which is one of the most popular algorithms to adjust the filter coefficient of an adaptive filter, is used. A model based design approach for the adaptive filter scheme is developed by using MATLAB, SIMULINK and SYSTEM GENERATOR which provides a virtual FPGA platform. The Filter is implemented using ALTERA Cyclone II FPGA KIT and the complete design cycle of Verilog Modeling, Coding, Simulation, Synthesis, Implementation; Testing on FPGA Target system is studied and practiced through the ADAPTIVE filter implementation. Simulation results of the conventional approach and model based design approach are compared for verification purpose.
Abstract— Electronics industry is very prodigiously moving
towards digital platform, but the worl... more Abstract— Electronics industry is very prodigiously moving towards digital platform, but the world is analog in nature, so when any analog signal needs to be processed in digital platform it should be converted to digital with the help of analog to digital converter. After processing through digital platform by the help of DAC it will be again converted to analog format. Here the digital platform is ALTERA CYCLONE-II FPGA. FIR filters are used in every aspect of present-day technology because filtering is one of the basic tools of information acquisition and manipulation. Different types of digital FIR filters are implemented on external signal by using VERILOG HDL language over FPGA. Further model based design approach using MATLAB and Simulink is taken into account for optimized designing and resource computation.
... Reconfiguration Sheetal U. Bhandari International Institute of Information Technology Pune, I... more ... Reconfiguration Sheetal U. Bhandari International Institute of Information Technology Pune, India sheetalb@isquareit.ac.in Shaila ... in Shashank Pujari International Institute of Information Technology Pune, India shashankp@isquareit.ac.in Abstract ...
Page 1. Embedding Driver for a Peripheral Interface on FPGA Sheetal U. Bhandari International Ins... more Page 1. Embedding Driver for a Peripheral Interface on FPGA Sheetal U. Bhandari International Institute of Information Technology, Pune (India) sheetalb@isquareit.ac.in Shashank Pujari International Institute of Information Technology, Pune (India) shashankp@isquareit.ac.in ...
An immobilizer is an electronic device fitted to an automobile which prevents the engine from run... more An immobilizer is an electronic device fitted to an automobile which prevents the engine from running unless the vehicle has the proper access to it. The main use of this system is to protect the vehicle from being stealth as it deactivates the engine. The immobilizer security ...
... Fly Partial Reconfiguration Sheetal U. Bhandari International Institute of Information Techno... more ... Fly Partial Reconfiguration Sheetal U. Bhandari International Institute of Information Technology Pune, India sheetalb@isquareit.ac.in ... shailasubbaraman@yahoo.co.in Shashank Pujari International Institute of Information Technology Pune, India shashankp@isquareit.ac.in ...
The paper covers a simple RTL implementation of a command processor with its associated macroinst... more The paper covers a simple RTL implementation of a command processor with its associated macroinstructions implemented on FPGA device to drive an external peripherals having processor like bus interface. Soft processor is used inside FPGA device to handle the tasks of software driver for peripheral controller. The paper discusses an approach to mimic a simple soft processor to handle the task at core layer of driver for basic communication with peripherals connected to FPGA. The present architecture envisages a three-tier implementation of peripheral hardware software co-design interface. The Top level is an application processor connected to FPGA for handling high-level application layers. The application processor could be a generic processor or a DSP. The next second level is a soft processor embedded in FPGA for handling middle layer software. Command processor or pre-processor handles the third bottom core layer task/command specific processing
—Adaptive Digital filter based on Least Mean Square (LMS) algorithm is widely used in the field o... more —Adaptive Digital filter based on Least Mean Square (LMS) algorithm is widely used in the field of Digital Signal processing to iteratively estimate the statistics of an unknown signal. Architecture of adaptive filter is based on three major computing elements namely multiplier, adder and delay unit to realize the Finite Impulse Response (FIR) filter. The coefficients of the FIR filter are adjusted automatically by LMS of the error so as to match the adapted output to the desired input. This paper explains the design of adaptive filter by two approaches. One is model based approach and other is Field Programmable Gate Arrays (FPGAs). The model based design approach is developed around MATLAB, SIMULINK and SYSTEM GENERATOR tools, which provide a virtual FPGA platform. Modern FPGA include the resources needed to design efficient filtering structures. The LMS algorithm has been implemented on CYCLONE II EP2C35F672C8 FPGA device, using ALTERA QUARTUS II development platform. The three major demonstrable applications cited in the present work are System Identification, Noise reduction and Echo cancellation.
System on programmable chip for the performance estimation of loom machine, which calculates the ... more System on programmable chip for the performance estimation of loom machine, which calculates the efficiency and meter count for weaved cloth automatically. Also it calculates the efficiency of loom machine. Previously the same was done using manual process which was not efficient. This article is intended for loom machines which are not modern.
2010 International Conference on Computer Applications and Industrial Electronics, 2010
... For Computation Intensive Applications on FPGA Sheetal Bhandari, Shashank Pujari,Avinash Inte... more ... For Computation Intensive Applications on FPGA Sheetal Bhandari, Shashank Pujari,Avinash International Institute of Information Technology Pune, India E-mail: (sheetalb, shashankp)@isquareit.ac.in, avinash_nov09@vlsi.isquareit.ac.in ...
Embedded Computing platforms based on
Microcontroller, Field Programmable Gate Array (FPGA) and
... more Embedded Computing platforms based on Microcontroller, Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) are subjects of interest at Under Graduate(UG) and Post Graduate(PG) levels in Electronics and Communication Engineering. Real Time Signal Processing algorithms are generally implemented on any one of these platforms. The paper presents a comparative performance analysis between Microcontroller and FPGA based signal processing by way of a case study on Finite Impulse Response (FIR) fIlter implementation. Microcontrollers are basically sequential and FPGAs are parallel computing platforms. This paper highlights the parallelism feature of FPGA to prove its efficiency against Microcontroller for signal processing applications.
With increased resource size, powerful DSP
blocks and large on-chip memory, Field Programmable Ga... more With increased resource size, powerful DSP blocks and large on-chip memory, Field Programmable Gate Array (FPGA) devices play a major role as hardware platforms for implementing compute intensive video image processing applications. In this paper, image processing algorithms are used for tracking a moving video object. The image processing algorithms used are (a) Noisy video generation with random motion (b) Video image median filter (c) Video image back ground removal (d) Video image thresholding (e) Video image edge detection (f) Video image height and width calculation (g) Video image center computation (h) Video image and center image overlay. The image processing algorithms are developed initially by Model Based Design Approach using Simulink models of MATHWORK’s MATLAB Tool. Then these algorithms are implemented on ALTERA CYCLONE-II FPGA device using TERASIC DE2 FPGA hardware kit and ALTERA QUARTUS-II software tool. The input video image is taken from a NTSC/PAL camera and processed in real time using the algorithms on the FPGA and the resulted tracked video image output is displayed on a VGA monitor.
Abstract— Filtering data in real-time requires dedicated
hardware to meet demanding time requirem... more Abstract— Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signals are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. Modern field programmable gate arrays (FPGAs) include the resources needed to design efficient filtering structures. The present work deals with the design and implementation of FPGA based adaptive filter for echo cancellation. Here LMS algorithm, which is one of the most popular algorithms to adjust the filter coefficient of an adaptive filter, is used. A model based design approach for the adaptive filter scheme is developed by using MATLAB, SIMULINK and SYSTEM GENERATOR which provides a virtual FPGA platform. The Filter is implemented using ALTERA Cyclone II FPGA KIT and the complete design cycle of Verilog Modeling, Coding, Simulation, Synthesis, Implementation; Testing on FPGA Target system is studied and practiced through the ADAPTIVE filter implementation. Simulation results of the conventional approach and model based design approach are compared for verification purpose.
Abstract— Electronics industry is very prodigiously moving
towards digital platform, but the worl... more Abstract— Electronics industry is very prodigiously moving towards digital platform, but the world is analog in nature, so when any analog signal needs to be processed in digital platform it should be converted to digital with the help of analog to digital converter. After processing through digital platform by the help of DAC it will be again converted to analog format. Here the digital platform is ALTERA CYCLONE-II FPGA. FIR filters are used in every aspect of present-day technology because filtering is one of the basic tools of information acquisition and manipulation. Different types of digital FIR filters are implemented on external signal by using VERILOG HDL language over FPGA. Further model based design approach using MATLAB and Simulink is taken into account for optimized designing and resource computation.
... Reconfiguration Sheetal U. Bhandari International Institute of Information Technology Pune, I... more ... Reconfiguration Sheetal U. Bhandari International Institute of Information Technology Pune, India sheetalb@isquareit.ac.in Shaila ... in Shashank Pujari International Institute of Information Technology Pune, India shashankp@isquareit.ac.in Abstract ...
Page 1. Embedding Driver for a Peripheral Interface on FPGA Sheetal U. Bhandari International Ins... more Page 1. Embedding Driver for a Peripheral Interface on FPGA Sheetal U. Bhandari International Institute of Information Technology, Pune (India) sheetalb@isquareit.ac.in Shashank Pujari International Institute of Information Technology, Pune (India) shashankp@isquareit.ac.in ...
An immobilizer is an electronic device fitted to an automobile which prevents the engine from run... more An immobilizer is an electronic device fitted to an automobile which prevents the engine from running unless the vehicle has the proper access to it. The main use of this system is to protect the vehicle from being stealth as it deactivates the engine. The immobilizer security ...
... Fly Partial Reconfiguration Sheetal U. Bhandari International Institute of Information Techno... more ... Fly Partial Reconfiguration Sheetal U. Bhandari International Institute of Information Technology Pune, India sheetalb@isquareit.ac.in ... shailasubbaraman@yahoo.co.in Shashank Pujari International Institute of Information Technology Pune, India shashankp@isquareit.ac.in ...
All in one slide for SET TOP BOX (STB) system. The single slide includes 19 different topics arou... more All in one slide for SET TOP BOX (STB) system. The single slide includes 19 different topics around STB, which could be further expanded. The motivation behind this slide is to apprise student community about convergence of variety of technologies towards a single Embedded Product Development around SET TOP BOX. Unfortunately SET TOP BOX is still a black box for the academic community. Can this gap be bridged ?
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Papers by Shashank Pujari
Microcontroller, Field Programmable Gate Array (FPGA) and
Digital Signal Processor (DSP) are subjects of interest at Under
Graduate(UG) and Post Graduate(PG) levels in Electronics and
Communication Engineering. Real Time Signal Processing
algorithms are generally implemented on any one of these
platforms. The paper presents a comparative performance
analysis between Microcontroller and FPGA based signal
processing by way of a case study on Finite Impulse Response
(FIR) fIlter implementation. Microcontrollers are basically
sequential and FPGAs are parallel computing platforms. This
paper highlights the parallelism feature of FPGA to prove its
efficiency against Microcontroller for signal processing
applications.
blocks and large on-chip memory, Field Programmable Gate
Array (FPGA) devices play a major role as hardware
platforms for implementing compute intensive video image
processing applications. In this paper, image processing
algorithms are used for tracking a moving video object. The
image processing algorithms used are (a) Noisy video
generation with random motion (b) Video image median
filter (c) Video image back ground removal (d) Video image
thresholding (e) Video image edge detection (f) Video image
height and width calculation (g) Video image center
computation (h) Video image and center image overlay. The
image processing algorithms are developed initially by
Model Based Design Approach using Simulink models of
MATHWORK’s MATLAB Tool. Then these algorithms are
implemented on ALTERA CYCLONE-II FPGA device using
TERASIC DE2 FPGA hardware kit and ALTERA
QUARTUS-II software tool. The input video image is taken
from a NTSC/PAL camera and processed in real time using
the algorithms on the FPGA and the resulted tracked video
image output is displayed on a VGA monitor.
hardware to meet demanding time requirements. If the statistics
of the signals are not known, then adaptive filtering algorithms
can be implemented to estimate the signals statistics iteratively.
Modern field programmable gate arrays (FPGAs) include the
resources needed to design efficient filtering structures. The
present work deals with the design and implementation of FPGA
based adaptive filter for echo cancellation. Here LMS algorithm,
which is one of the most popular algorithms to adjust the filter
coefficient of an adaptive filter, is used. A model based design
approach for the adaptive filter scheme is developed by using
MATLAB, SIMULINK and SYSTEM GENERATOR which
provides a virtual FPGA platform. The Filter is implemented
using ALTERA Cyclone II FPGA KIT and the complete design
cycle of Verilog Modeling, Coding, Simulation, Synthesis,
Implementation; Testing on FPGA Target system is studied and
practiced through the ADAPTIVE filter implementation.
Simulation results of the conventional approach and model based
design approach are compared for verification purpose.
towards digital platform, but the world is analog in nature, so
when any analog signal needs to be processed in digital platform
it should be converted to digital with the help of analog to digital
converter. After processing through digital platform by the help
of DAC it will be again converted to analog format. Here the
digital platform is ALTERA CYCLONE-II FPGA. FIR filters are
used in every aspect of present-day technology because filtering is
one of the basic tools of information acquisition and
manipulation. Different types of digital FIR filters are
implemented on external signal by using VERILOG HDL
language over FPGA. Further model based design approach
using MATLAB and Simulink is taken into account for
optimized designing and resource computation.
Microcontroller, Field Programmable Gate Array (FPGA) and
Digital Signal Processor (DSP) are subjects of interest at Under
Graduate(UG) and Post Graduate(PG) levels in Electronics and
Communication Engineering. Real Time Signal Processing
algorithms are generally implemented on any one of these
platforms. The paper presents a comparative performance
analysis between Microcontroller and FPGA based signal
processing by way of a case study on Finite Impulse Response
(FIR) fIlter implementation. Microcontrollers are basically
sequential and FPGAs are parallel computing platforms. This
paper highlights the parallelism feature of FPGA to prove its
efficiency against Microcontroller for signal processing
applications.
blocks and large on-chip memory, Field Programmable Gate
Array (FPGA) devices play a major role as hardware
platforms for implementing compute intensive video image
processing applications. In this paper, image processing
algorithms are used for tracking a moving video object. The
image processing algorithms used are (a) Noisy video
generation with random motion (b) Video image median
filter (c) Video image back ground removal (d) Video image
thresholding (e) Video image edge detection (f) Video image
height and width calculation (g) Video image center
computation (h) Video image and center image overlay. The
image processing algorithms are developed initially by
Model Based Design Approach using Simulink models of
MATHWORK’s MATLAB Tool. Then these algorithms are
implemented on ALTERA CYCLONE-II FPGA device using
TERASIC DE2 FPGA hardware kit and ALTERA
QUARTUS-II software tool. The input video image is taken
from a NTSC/PAL camera and processed in real time using
the algorithms on the FPGA and the resulted tracked video
image output is displayed on a VGA monitor.
hardware to meet demanding time requirements. If the statistics
of the signals are not known, then adaptive filtering algorithms
can be implemented to estimate the signals statistics iteratively.
Modern field programmable gate arrays (FPGAs) include the
resources needed to design efficient filtering structures. The
present work deals with the design and implementation of FPGA
based adaptive filter for echo cancellation. Here LMS algorithm,
which is one of the most popular algorithms to adjust the filter
coefficient of an adaptive filter, is used. A model based design
approach for the adaptive filter scheme is developed by using
MATLAB, SIMULINK and SYSTEM GENERATOR which
provides a virtual FPGA platform. The Filter is implemented
using ALTERA Cyclone II FPGA KIT and the complete design
cycle of Verilog Modeling, Coding, Simulation, Synthesis,
Implementation; Testing on FPGA Target system is studied and
practiced through the ADAPTIVE filter implementation.
Simulation results of the conventional approach and model based
design approach are compared for verification purpose.
towards digital platform, but the world is analog in nature, so
when any analog signal needs to be processed in digital platform
it should be converted to digital with the help of analog to digital
converter. After processing through digital platform by the help
of DAC it will be again converted to analog format. Here the
digital platform is ALTERA CYCLONE-II FPGA. FIR filters are
used in every aspect of present-day technology because filtering is
one of the basic tools of information acquisition and
manipulation. Different types of digital FIR filters are
implemented on external signal by using VERILOG HDL
language over FPGA. Further model based design approach
using MATLAB and Simulink is taken into account for
optimized designing and resource computation.