2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009
A bang-bang delay-locked loop based on a digital filter and a DAC controlling the line delay suff... more A bang-bang delay-locked loop based on a digital filter and a DAC controlling the line delay suffers from the presence of a limit cycle that produces periodic jitter. A tight trade-off exists between jitter and DAC resolution. This paper proposes an all-digital architecture of regulated delay line based on a digital first-order ¿¿ modulator and a single-bit DAC, which eliminates the need for the high-resolution DAC and trades jitter against bandwidth. A theoretical estimation of the jitter induced by the ¿¿ quantization noise is provided. The realized delay-locked loop generates 16 phases of the 3-4 GHz input signal in a 90-nm CMOS technology. The simulated delay jitter of 30 fs rms confirms the theoretical estimation.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2000
... Based on a Digital Bang-Bang DLL Marco Zanuso, Student Member, IEEE, Paolo Madoglio, Student ... more ... Based on a Digital Bang-Bang DLL Marco Zanuso, Student Member, IEEE, Paolo Madoglio, Student Member, IEEE, Salvatore Levantino, Member, IEEE, Carlo Samori, Senior Member, IEEE, and Andrea L. Lacaita, Fellow, IEEE ... The limit-cycle-induced spur is below 50 dBc. ...
2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011
This work describes an original behavioral simula- tion method for the phase-noise analysis of ch... more This work describes an original behavioral simula- tion method for the phase-noise analysis of charge-pump phase- locked-loops. The method provides a numerically efficient way to evaluate the in-band output noise which is found when a frequency divider is present in the loop. I. INTRODUCTION Noise performance in nonlinear Phase-Locked-Loops (PLLs) are of great concern. In particular, in this paper we focus on the phase-noise analysis of the popular integer-N Charge-Pump third order PLL (CP-PLL) shown in Fig. 1. This PLL is composed by a phase/frequency detector (PFD) that detects the phase difference between the reference (ref) and the feedback (div) signals at the rising edges of the related waveforms and injects, via a charge pump (CP) a proportional charge into the passive loop filter. Owing to the "sampling operation" of the PFD, to the wide bandwidth of the loop (as compared to the input reference signal) and to the presence of a frequency divider in the feedback path, the analysis and simulation of this circuit results particularly challenging. In fact, the time-varying nature of the CP-PLL makes the conventional methodology analysis based on the continuous- time approximation and Laplace's transform not applicable anymore (1). Under the assumption that the duration of the pulses generated by the CP is much smaller than the oscillator period, the PLL operation can be approximated as that of a discrete-time system and modelled in the z-domain (2), (3), (4). Methods based on z-domain model have been successfully adopted to evaluate the stability properties of CP-PLLs, how- ever their extension to determine the noise transfer functions is not straightforward when the PLL contains a frequency divider. In this case, two frequency domains exist in the loop (one operating at the reference frequency and the other at the output frequency) and this can result in an extra in-band noise component due to the folding of the VCO phase-noise spectrum (5).
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009
A bang-bang delay-locked loop based on a digital filter and a DAC controlling the line delay suff... more A bang-bang delay-locked loop based on a digital filter and a DAC controlling the line delay suffers from the presence of a limit cycle that produces periodic jitter. A tight trade-off exists between jitter and DAC resolution. This paper proposes an all-digital architecture of regulated delay line based on a digital first-order ¿¿ modulator and a single-bit DAC, which eliminates the need for the high-resolution DAC and trades jitter against bandwidth. A theoretical estimation of the jitter induced by the ¿¿ quantization noise is provided. The realized delay-locked loop generates 16 phases of the 3-4 GHz input signal in a 90-nm CMOS technology. The simulated delay jitter of 30 fs rms confirms the theoretical estimation.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2000
... Based on a Digital Bang-Bang DLL Marco Zanuso, Student Member, IEEE, Paolo Madoglio, Student ... more ... Based on a Digital Bang-Bang DLL Marco Zanuso, Student Member, IEEE, Paolo Madoglio, Student Member, IEEE, Salvatore Levantino, Member, IEEE, Carlo Samori, Senior Member, IEEE, and Andrea L. Lacaita, Fellow, IEEE ... The limit-cycle-induced spur is below 50 dBc. ...
2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011
This work describes an original behavioral simula- tion method for the phase-noise analysis of ch... more This work describes an original behavioral simula- tion method for the phase-noise analysis of charge-pump phase- locked-loops. The method provides a numerically efficient way to evaluate the in-band output noise which is found when a frequency divider is present in the loop. I. INTRODUCTION Noise performance in nonlinear Phase-Locked-Loops (PLLs) are of great concern. In particular, in this paper we focus on the phase-noise analysis of the popular integer-N Charge-Pump third order PLL (CP-PLL) shown in Fig. 1. This PLL is composed by a phase/frequency detector (PFD) that detects the phase difference between the reference (ref) and the feedback (div) signals at the rising edges of the related waveforms and injects, via a charge pump (CP) a proportional charge into the passive loop filter. Owing to the "sampling operation" of the PFD, to the wide bandwidth of the loop (as compared to the input reference signal) and to the presence of a frequency divider in the feedback path, the analysis and simulation of this circuit results particularly challenging. In fact, the time-varying nature of the CP-PLL makes the conventional methodology analysis based on the continuous- time approximation and Laplace's transform not applicable anymore (1). Under the assumption that the duration of the pulses generated by the CP is much smaller than the oscillator period, the PLL operation can be approximated as that of a discrete-time system and modelled in the z-domain (2), (3), (4). Methods based on z-domain model have been successfully adopted to evaluate the stability properties of CP-PLLs, how- ever their extension to determine the noise transfer functions is not straightforward when the PLL contains a frequency divider. In this case, two frequency domains exist in the loop (one operating at the reference frequency and the other at the output frequency) and this can result in an extra in-band noise component due to the folding of the VCO phase-noise spectrum (5).
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Papers by C. Samori