2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
The work in this paper centres around comparison amongst conventional and RHBD technique based co... more The work in this paper centres around comparison amongst conventional and RHBD technique based combinational and sequential standard cells in 0.18μmCMOS technology using SCL PDK in Cadence Virtuoso. In space radioactive particles (proton, neutrons, $\alpha$) and heavy ions makes the biggest threat to Integrated Circuits (IC). With continuously decreasing feature size and lowering of the supply voltage, causes Single Event Transients (SETs) which is becoming a major problem for both combinational and sequential digital circuits in the Deep Submicron technology (DSM). The proposed C- element based cells investigated are Inverter, NAND gate, Buffer and D-Flip Flop. Schematic and layout of these cells are developed using Cadence Virtuoso tool. Circuits which are designed with the RHBD approaches are more tolerant to Single Event Effects (SEE), have better noise immunity and less static power consumption. The reduction in the average power in proposed style is 94% and the delay reduction...
2022 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)
The thermal influence of the self-heating (SH) effect in electronic devices on interconnects is e... more The thermal influence of the self-heating (SH) effect in electronic devices on interconnects is explored in this paper. The self-heating effect in these devices will generate greater heat in structures, which may affect interconnect dependability. The RedHawk Tool is used to examine a chip design provided by STMicroelectronics in this study. Temperature variations in distinct metal layers, and self-heating impact are all part of the evaluation. Earlier technology didn't include the delta $T$ modelling in the design which is being considered here. Concept of de-coupling capacitors are employed to reduce power consumption in the design.
Intelligent Computing and Information and Communication, 2018
This paper introduces high-performance pipelined 256-point FFT processor based on Radix-22 for OF... more This paper introduces high-performance pipelined 256-point FFT processor based on Radix-22 for OFDM communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm. Radix-2 butterfly’s complexity is very low and Radix-22 CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. The proposed design is implemented in VHDL language, synthesized using XST of Xilinx ISE 14.1, and simulated using ModelSim PE Student Edition 10.4a successfully. Also, MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 129.214 MHz after the synthesis process and SQNR is 50.95 dB.
2017 4th International Conference on Signal Processing and Integrated Networks (SPIN), 2017
This Paper presents high Speed pipeline 64-point FFT processor based on Radix-22 for wireless LAN... more This Paper presents high Speed pipeline 64-point FFT processor based on Radix-22 for wireless LAN communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm. Radix-2 butterfly's complexity is very low and Radix-22 CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. An efficient VHDL code has been written, synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModelSim PE Student Edition 10.4a. Also MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 158.96 MHz after the synthesis process and SQNR 37.02dB for 64 point.
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), 2017
Single event transients (SETs) have become increasingly problematic for both combinational and se... more Single event transients (SETs) have become increasingly problematic for both combinational and sequential VLSI circuits in the deep submicron technology (DSM). This is due to continuously decreasing feature sizes, lower supply voltages and higher operating frequencies. Many critical applications such as biomedical, space and military electronics as well as several mainstream computing applications demand reliable circuit functionality. Therefore, the circuits used in these application must be tolerant to SEU/SET events and therefore, these circuits are designed using circuit hardening approaches. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on combinational logic circuits. It presents a Radiation Hardened By Design (RHBD) of combinational circuits using 0.18μm technology and developed with the help of Cadence tool. This design style achieves SET mitigation by using C element and strengthening the sensitive output node. In order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability with minimum area, power and speed penalties.
In this paper, an improved gain CMOS Low Noise Amplifier (LNA) is presented. Here a single stage ... more In this paper, an improved gain CMOS Low Noise Amplifier (LNA) is presented. Here a single stage common source amplifier with common gate as cascode circuit is used to design the LNA. It is having small signal gain of 14.4 dB and covers the bandwidth from 4.47 GHz to 5.41 GHz. It has been observed that at the center frequency of 5 GHz the input and output return loss are −17.98 dB and −15.86 dB respectively. A 1 dB compression point is at −14.85 dBm at 5 GHz input frequency. From 1.8 V supply voltage, 4.67 mA current is drawn.
2018 15th IEEE India Council International Conference (INDICON), 2018
in this paper a body biased NMOS as frequency-tuning technique is proposed for 60 GHz Voltage Con... more in this paper a body biased NMOS as frequency-tuning technique is proposed for 60 GHz Voltage Controlled Oscillator (VCO) design. The proposed technique is implemented in 130 nm CMOS RF technology. A simplified analytical model using simple body biased NMOS is used to tune the frequency of the VCO. With 0.8 V of supply voltage, proposed tuning technique provides a frequency tuning range from 57 GHz to 62 GHz, i.e. 8.4 % of Frequency Tuning Range (FTR) with center frequency of 59.5 GHz is obtained. Phase noise at 10 MHz offset from 62 GHz oscillation frequency is -119.42 dBc/Hz. Calculated Figure of Merit (FoM) is -187.21 dBc/Hz
Engineering Science and Technology, an International Journal, 2021
Abstract With the advancements of communication technology, security threats are also increasing.... more Abstract With the advancements of communication technology, security threats are also increasing. RSA is a robust cryptosystem to protect classified information. The efficiency of RSA cryptosystem depends on the efficient execution of Montgomery modular multiplication. A low latency and throughput efficient Montgomery modular multiplier is proposed in this paper. The input and final output of this multiplier are binary, but intermediate input and output are carry-saved i.e. sum and carry bits are stored in separate registers. Sum and carry bits are obtained from the addition of operands using carry-save adder (CSA). Montgomery multipliers require quotient calculation for subsequent iteration. The proposed multiplier computes two subsequent quotients in parallel with carry-save addition. Output of carry-save addition is right shifted by two bits to obtain the next-to-next intermediate output. This calculation also requires integer multiples of the inputs. Computation of next output is skipped. Format conversion of output is performed using a carry look-ahead unit (CLU). CLU along with one cycle of carry save addition is also utilized for pre-computation of integer multiples of inputs. The proposed multiplier is implemented on NEXYS4DDR and VIRTEX VII FPGA and the following result is obtained. NEXYS4DDR: Area (LUT + REG): 38903, Delay: 5.84 ns, Cycles: 1158, Latency: 6.76 µs, Throughput: 302.96 Mbps. VIRTEX VII: Area (LUT): 16447, Delay: 1.62 ns, Cycles: 1158, Latency: 1.88 µs, Throughput: 1089.4 Mbps. Results verify the improved area, latency and throughput performance of the proposed work.
In this work a novel inductive tuning technique for millimeter wave (mmw) applications is present... more In this work a novel inductive tuning technique for millimeter wave (mmw) applications is presented. Fine frequency tuning is performed using a transformer. For the LC tanks inductive element, transformer is used. To tune the VCO MOS switch is placed at center tapping of the secondary coil of the transformer. The simulation shows that by changing the operating condition of MOS switch frequency band from 59.1 GHz to 64.6 GHz is obtained. The proposed 60 GHz VCO is designed using UMC 65 nm CMOS single Poly eight Metal (1P8M) Technology. Obtained Frequency Tuning Range (FTR) is 8.89% and the corresponding phase noise variation is from − 112.4 dBc/Hz to − 115.9 dBc/Hz at 10 MHz offset from the carrier. The worst phase noise value is − 112.4 dBc/Hz which is obtained at 0.3 V tuning voltage. For 0.8 V supply voltage 7.44 mW of power is dissipated. And the calculated Figure of Merit (FOM) for whole FTR, ranges from − 179.89 dBc/Hz to − 182.62 dBc/Hz.
A high-speed Montgomery modular multiplier is proposed in this study. This multiplier requires bi... more A high-speed Montgomery modular multiplier is proposed in this study. This multiplier requires binary input and also generates a modular product in binary form. To speed up the process of multiplication, intermediate operands of the multiplier are kept in carry-save form. This multiplier employs a two-level carry-save adder architecture to keep intermediate operands in carry-save form. This multiplier also employs a look-ahead carry unit (LCU) for conversion of the final output from carry-save form to binary form. LCU is also utilised for pre-computation of intermediate operands. Format conversion and pre-computation require additional clock cycles. In general, each cycle of the Montgomery multipliers involves addition and shift operation followed by computation of the following quotient. The proposed multiplier adds and shifts as well as computes the following two quotients simultaneously to minimise the critical path delay. In addition, the proposed multiplier combines two iterations, which require additional intermediate operands. In this way, the execution time and the number of clock cycles required for multiplication are minimised significantly and extra clock cycles required for format conversion and operand pre-computation can be overlooked. Experimental results show that the proposed approach can achieve significant speed and throughput improvement as compared to previous multipliers.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
The work in this paper centres around comparison amongst conventional and RHBD technique based co... more The work in this paper centres around comparison amongst conventional and RHBD technique based combinational and sequential standard cells in 0.18μmCMOS technology using SCL PDK in Cadence Virtuoso. In space radioactive particles (proton, neutrons, $\alpha$) and heavy ions makes the biggest threat to Integrated Circuits (IC). With continuously decreasing feature size and lowering of the supply voltage, causes Single Event Transients (SETs) which is becoming a major problem for both combinational and sequential digital circuits in the Deep Submicron technology (DSM). The proposed C- element based cells investigated are Inverter, NAND gate, Buffer and D-Flip Flop. Schematic and layout of these cells are developed using Cadence Virtuoso tool. Circuits which are designed with the RHBD approaches are more tolerant to Single Event Effects (SEE), have better noise immunity and less static power consumption. The reduction in the average power in proposed style is 94% and the delay reduction...
2022 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)
The thermal influence of the self-heating (SH) effect in electronic devices on interconnects is e... more The thermal influence of the self-heating (SH) effect in electronic devices on interconnects is explored in this paper. The self-heating effect in these devices will generate greater heat in structures, which may affect interconnect dependability. The RedHawk Tool is used to examine a chip design provided by STMicroelectronics in this study. Temperature variations in distinct metal layers, and self-heating impact are all part of the evaluation. Earlier technology didn't include the delta $T$ modelling in the design which is being considered here. Concept of de-coupling capacitors are employed to reduce power consumption in the design.
Intelligent Computing and Information and Communication, 2018
This paper introduces high-performance pipelined 256-point FFT processor based on Radix-22 for OF... more This paper introduces high-performance pipelined 256-point FFT processor based on Radix-22 for OFDM communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm. Radix-2 butterfly’s complexity is very low and Radix-22 CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. The proposed design is implemented in VHDL language, synthesized using XST of Xilinx ISE 14.1, and simulated using ModelSim PE Student Edition 10.4a successfully. Also, MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 129.214 MHz after the synthesis process and SQNR is 50.95 dB.
2017 4th International Conference on Signal Processing and Integrated Networks (SPIN), 2017
This Paper presents high Speed pipeline 64-point FFT processor based on Radix-22 for wireless LAN... more This Paper presents high Speed pipeline 64-point FFT processor based on Radix-22 for wireless LAN communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm. Radix-2 butterfly's complexity is very low and Radix-22 CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. An efficient VHDL code has been written, synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModelSim PE Student Edition 10.4a. Also MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 158.96 MHz after the synthesis process and SQNR 37.02dB for 64 point.
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), 2017
Single event transients (SETs) have become increasingly problematic for both combinational and se... more Single event transients (SETs) have become increasingly problematic for both combinational and sequential VLSI circuits in the deep submicron technology (DSM). This is due to continuously decreasing feature sizes, lower supply voltages and higher operating frequencies. Many critical applications such as biomedical, space and military electronics as well as several mainstream computing applications demand reliable circuit functionality. Therefore, the circuits used in these application must be tolerant to SEU/SET events and therefore, these circuits are designed using circuit hardening approaches. Hardening by design techniques based on increasing the amount of charge representing the bit and redundancy techniques have been used over the years. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on combinational logic circuits. It presents a Radiation Hardened By Design (RHBD) of combinational circuits using 0.18μm technology and developed with the help of Cadence tool. This design style achieves SET mitigation by using C element and strengthening the sensitive output node. In order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability with minimum area, power and speed penalties.
In this paper, an improved gain CMOS Low Noise Amplifier (LNA) is presented. Here a single stage ... more In this paper, an improved gain CMOS Low Noise Amplifier (LNA) is presented. Here a single stage common source amplifier with common gate as cascode circuit is used to design the LNA. It is having small signal gain of 14.4 dB and covers the bandwidth from 4.47 GHz to 5.41 GHz. It has been observed that at the center frequency of 5 GHz the input and output return loss are −17.98 dB and −15.86 dB respectively. A 1 dB compression point is at −14.85 dBm at 5 GHz input frequency. From 1.8 V supply voltage, 4.67 mA current is drawn.
2018 15th IEEE India Council International Conference (INDICON), 2018
in this paper a body biased NMOS as frequency-tuning technique is proposed for 60 GHz Voltage Con... more in this paper a body biased NMOS as frequency-tuning technique is proposed for 60 GHz Voltage Controlled Oscillator (VCO) design. The proposed technique is implemented in 130 nm CMOS RF technology. A simplified analytical model using simple body biased NMOS is used to tune the frequency of the VCO. With 0.8 V of supply voltage, proposed tuning technique provides a frequency tuning range from 57 GHz to 62 GHz, i.e. 8.4 % of Frequency Tuning Range (FTR) with center frequency of 59.5 GHz is obtained. Phase noise at 10 MHz offset from 62 GHz oscillation frequency is -119.42 dBc/Hz. Calculated Figure of Merit (FoM) is -187.21 dBc/Hz
Engineering Science and Technology, an International Journal, 2021
Abstract With the advancements of communication technology, security threats are also increasing.... more Abstract With the advancements of communication technology, security threats are also increasing. RSA is a robust cryptosystem to protect classified information. The efficiency of RSA cryptosystem depends on the efficient execution of Montgomery modular multiplication. A low latency and throughput efficient Montgomery modular multiplier is proposed in this paper. The input and final output of this multiplier are binary, but intermediate input and output are carry-saved i.e. sum and carry bits are stored in separate registers. Sum and carry bits are obtained from the addition of operands using carry-save adder (CSA). Montgomery multipliers require quotient calculation for subsequent iteration. The proposed multiplier computes two subsequent quotients in parallel with carry-save addition. Output of carry-save addition is right shifted by two bits to obtain the next-to-next intermediate output. This calculation also requires integer multiples of the inputs. Computation of next output is skipped. Format conversion of output is performed using a carry look-ahead unit (CLU). CLU along with one cycle of carry save addition is also utilized for pre-computation of integer multiples of inputs. The proposed multiplier is implemented on NEXYS4DDR and VIRTEX VII FPGA and the following result is obtained. NEXYS4DDR: Area (LUT + REG): 38903, Delay: 5.84 ns, Cycles: 1158, Latency: 6.76 µs, Throughput: 302.96 Mbps. VIRTEX VII: Area (LUT): 16447, Delay: 1.62 ns, Cycles: 1158, Latency: 1.88 µs, Throughput: 1089.4 Mbps. Results verify the improved area, latency and throughput performance of the proposed work.
In this work a novel inductive tuning technique for millimeter wave (mmw) applications is present... more In this work a novel inductive tuning technique for millimeter wave (mmw) applications is presented. Fine frequency tuning is performed using a transformer. For the LC tanks inductive element, transformer is used. To tune the VCO MOS switch is placed at center tapping of the secondary coil of the transformer. The simulation shows that by changing the operating condition of MOS switch frequency band from 59.1 GHz to 64.6 GHz is obtained. The proposed 60 GHz VCO is designed using UMC 65 nm CMOS single Poly eight Metal (1P8M) Technology. Obtained Frequency Tuning Range (FTR) is 8.89% and the corresponding phase noise variation is from − 112.4 dBc/Hz to − 115.9 dBc/Hz at 10 MHz offset from the carrier. The worst phase noise value is − 112.4 dBc/Hz which is obtained at 0.3 V tuning voltage. For 0.8 V supply voltage 7.44 mW of power is dissipated. And the calculated Figure of Merit (FOM) for whole FTR, ranges from − 179.89 dBc/Hz to − 182.62 dBc/Hz.
A high-speed Montgomery modular multiplier is proposed in this study. This multiplier requires bi... more A high-speed Montgomery modular multiplier is proposed in this study. This multiplier requires binary input and also generates a modular product in binary form. To speed up the process of multiplication, intermediate operands of the multiplier are kept in carry-save form. This multiplier employs a two-level carry-save adder architecture to keep intermediate operands in carry-save form. This multiplier also employs a look-ahead carry unit (LCU) for conversion of the final output from carry-save form to binary form. LCU is also utilised for pre-computation of intermediate operands. Format conversion and pre-computation require additional clock cycles. In general, each cycle of the Montgomery multipliers involves addition and shift operation followed by computation of the following quotient. The proposed multiplier adds and shifts as well as computes the following two quotients simultaneously to minimise the critical path delay. In addition, the proposed multiplier combines two iterations, which require additional intermediate operands. In this way, the execution time and the number of clock cycles required for multiplication are minimised significantly and extra clock cycles required for format conversion and operand pre-computation can be overlooked. Experimental results show that the proposed approach can achieve significant speed and throughput improvement as compared to previous multipliers.
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