The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out ... more The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out and the results have been interpreted with the help of a numerical solution to the one-dimensional Laplace-Poisson's equation. Various parameters characterizing the SOI MOS structures have been extracted. It has been shown that the C-V data on a simple three-terminal SOI MOS capacitor structure can
Millimeter-wave (mm-wave) bandpass filters are pre- sented using the standard 0.18-µm CMOS proces... more Millimeter-wave (mm-wave) bandpass filters are pre- sented using the standard 0.18-µm CMOS process. Without any postprocessing steps, thin film microstrip (TFMS) structure is properly constructed on the low-resistivity silicon substrate, aim- ing at reducing the substrate loss and crosstalk to a large extent. Using the broadside-coupled scheme, a tight coupling is achieved so as to make up a class of low-loss and broadband TFMS bandpass filters in the mm-wave range. To achieve a small size, one-stage and two-stage filters with sinuous-shaped resonators are designed and fabricated. A good agreement between the predicted and measured results has been observed up to 110 GHz. Index Terms—Bandpass filter, millimeter-wave (mm-wave), silicon substrate, thin film microstrip (TFMS) line.
The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out ... more The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out and the results have been interpreted with the help of a numerical solution to the one-dimensional Laplao+Poisson's equation. Various parameters characterizing the SOI MOS structures have been extracted. It has been shown that the C-V data on a simple three-terminal SOI MOS capacitor structure can yield all the information such as the thickness of the gate oxide, buried-oxide as well as the SO1 film, along with the doping density in the tilm and the substrate. I. iNTRODUCTION
An empirical model for a MOS varactor, valid in both the accumulation and depletion regions of bi... more An empirical model for a MOS varactor, valid in both the accumulation and depletion regions of bias over the R F frequency range up to IOGHz, is proposed. Measured data that verify the model are presented. The model is found to be valid over a wide range of MOS varactor layouts dimensions and can be easily tuned to different processes.
Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, 2008
Charge-Based Capacitance Measurement (CBCM) techniques are promising not only for small size inte... more Charge-Based Capacitance Measurement (CBCM) techniques are promising not only for small size interconnects [1] but also for small capacitance of active devices [2].[3]. In this paper, the factors that decide the lower limits of measurements as well as the sources of errors are evaluated based on extensive mixed device and circuit mode simulations. The role of the parasitic capacitance of the source/drain terminals of the devices constituting the pseudo-inverter is clearly delineated. INTRODUCTION Accurate measurement of ultra-small capacitance is crucial to successful device characterization and development of compact models for circuit applications of the next-generation nanoscale devices. Direct AC small signal measurements is extremely challenging when capacitance of device under test (DUT) falls below tens of femto-farads [4]. CBCM technique, originally proposed by Chen et al. for passive interconnect capacitance measurement [1], has recently been used for characterizing the non-linear gate capacitance of MOS devices [2][3]. As shown in Fig. 1, the capacitance C DUT is given by the difference in the average current between the test branch loaded with DUT, I Vdd , and the current in the reference branch, I' Vdd .
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03, 2003
A 11: ?.4GHz fully integi-ated CMOS Low Noise Amplifier (LNA) including the 500 referenced input ... more A 11: ?.4GHz fully integi-ated CMOS Low Noise Amplifier (LNA) including the 500 referenced input output matching networks is implemented using 0. ISpin technology within a chip area of4.1mm2. The amplifier h k the noise figure (NF) of 3.8dB and a forward gain of more tlian ZOdB. The details ofthe LNA analysis and design procedure are presented in this paper.
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 2000
This paper presents a simple scheme for estimating the digital switching noise at the sensitive R... more This paper presents a simple scheme for estimating the digital switching noise at the sensitive RF nodes with the help of a lumped element model for the substrate network. The model parameters have been extracted from the 2-port RF measurements. The efficacy of different isolation schemes such as grounded P+ guard bars and deep N-well has been investigated using phase
ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007
In this paper, an S-parameter measurement based modeling methodology is proposed for characteriza... more In this paper, an S-parameter measurement based modeling methodology is proposed for characterization of coupled interconnects on silicon substrate. First, a set of single transmission lines in ground-signal-ground configuration is measured and modeled as multiple Γ-sections. A pair of coupled lines is then modeled as two single lines interconnected by coupling capacitance, mutual inductance and mutual resistance. Asymptotic techniques and closed-form analytical expressions are used to determine the initial guesses for optimization of the model parameters of single and coupled lines. It is found that in extending the single line model to the coupled lines, only a couple of model parameters need to change due to the proximity effect. Further, the time-domain crosstalk is measured for Cu/oxide and Cu/Ultra low-κ interconnects and analyzed using the proposed model. Good agreement is found between the simulated and measured results in both the frequency and the time domains for different lengths, widths and spacing (for coupled-lines) confirming the accuracy of the modeling methodology. The compact modeling approach presented here facilitates accurate characterization and modeling of coupled interconnects based on measured S-parameters data.
The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out ... more The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out and the results have been interpreted with the help of a numerical solution to the one-dimensional Laplace-Poisson's equation. Various parameters characterizing the SOI MOS structures have been extracted. It has been shown that the C-V data on a simple three-terminal SOI MOS capacitor structure can
Millimeter-wave (mm-wave) bandpass filters are pre- sented using the standard 0.18-µm CMOS proces... more Millimeter-wave (mm-wave) bandpass filters are pre- sented using the standard 0.18-µm CMOS process. Without any postprocessing steps, thin film microstrip (TFMS) structure is properly constructed on the low-resistivity silicon substrate, aim- ing at reducing the substrate loss and crosstalk to a large extent. Using the broadside-coupled scheme, a tight coupling is achieved so as to make up a class of low-loss and broadband TFMS bandpass filters in the mm-wave range. To achieve a small size, one-stage and two-stage filters with sinuous-shaped resonators are designed and fabricated. A good agreement between the predicted and measured results has been observed up to 110 GHz. Index Terms—Bandpass filter, millimeter-wave (mm-wave), silicon substrate, thin film microstrip (TFMS) line.
The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out ... more The capacitance-voltage characterization of a MOS structure in the SOI film has been carried out and the results have been interpreted with the help of a numerical solution to the one-dimensional Laplao+Poisson's equation. Various parameters characterizing the SOI MOS structures have been extracted. It has been shown that the C-V data on a simple three-terminal SOI MOS capacitor structure can yield all the information such as the thickness of the gate oxide, buried-oxide as well as the SO1 film, along with the doping density in the tilm and the substrate. I. iNTRODUCTION
An empirical model for a MOS varactor, valid in both the accumulation and depletion regions of bi... more An empirical model for a MOS varactor, valid in both the accumulation and depletion regions of bias over the R F frequency range up to IOGHz, is proposed. Measured data that verify the model are presented. The model is found to be valid over a wide range of MOS varactor layouts dimensions and can be easily tuned to different processes.
Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, 2008
Charge-Based Capacitance Measurement (CBCM) techniques are promising not only for small size inte... more Charge-Based Capacitance Measurement (CBCM) techniques are promising not only for small size interconnects [1] but also for small capacitance of active devices [2].[3]. In this paper, the factors that decide the lower limits of measurements as well as the sources of errors are evaluated based on extensive mixed device and circuit mode simulations. The role of the parasitic capacitance of the source/drain terminals of the devices constituting the pseudo-inverter is clearly delineated. INTRODUCTION Accurate measurement of ultra-small capacitance is crucial to successful device characterization and development of compact models for circuit applications of the next-generation nanoscale devices. Direct AC small signal measurements is extremely challenging when capacitance of device under test (DUT) falls below tens of femto-farads [4]. CBCM technique, originally proposed by Chen et al. for passive interconnect capacitance measurement [1], has recently been used for characterizing the non-linear gate capacitance of MOS devices [2][3]. As shown in Fig. 1, the capacitance C DUT is given by the difference in the average current between the test branch loaded with DUT, I Vdd , and the current in the reference branch, I' Vdd .
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03, 2003
A 11: ?.4GHz fully integi-ated CMOS Low Noise Amplifier (LNA) including the 500 referenced input ... more A 11: ?.4GHz fully integi-ated CMOS Low Noise Amplifier (LNA) including the 500 referenced input output matching networks is implemented using 0. ISpin technology within a chip area of4.1mm2. The amplifier h k the noise figure (NF) of 3.8dB and a forward gain of more tlian ZOdB. The details ofthe LNA analysis and design procedure are presented in this paper.
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 2000
This paper presents a simple scheme for estimating the digital switching noise at the sensitive R... more This paper presents a simple scheme for estimating the digital switching noise at the sensitive RF nodes with the help of a lumped element model for the substrate network. The model parameters have been extracted from the 2-port RF measurements. The efficacy of different isolation schemes such as grounded P+ guard bars and deep N-well has been investigated using phase
ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007
In this paper, an S-parameter measurement based modeling methodology is proposed for characteriza... more In this paper, an S-parameter measurement based modeling methodology is proposed for characterization of coupled interconnects on silicon substrate. First, a set of single transmission lines in ground-signal-ground configuration is measured and modeled as multiple Γ-sections. A pair of coupled lines is then modeled as two single lines interconnected by coupling capacitance, mutual inductance and mutual resistance. Asymptotic techniques and closed-form analytical expressions are used to determine the initial guesses for optimization of the model parameters of single and coupled lines. It is found that in extending the single line model to the coupled lines, only a couple of model parameters need to change due to the proximity effect. Further, the time-domain crosstalk is measured for Cu/oxide and Cu/Ultra low-κ interconnects and analyzed using the proposed model. Good agreement is found between the simulated and measured results in both the frequency and the time domains for different lengths, widths and spacing (for coupled-lines) confirming the accuracy of the modeling methodology. The compact modeling approach presented here facilitates accurate characterization and modeling of coupled interconnects based on measured S-parameters data.
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Papers by Subhash Rustagi