Toufik Djeradi

The Network on-Chip (NoC) is considered as an emerging technology for distributed embedded systems which is proposed as an alternative interconnection solution in Mutli-Processors System on-Chip (MPSoC). This paper proposes a graphical toll that allows researchers to generate and configure quickly their Network on-Chip in the hope to evaluate easily their contributions in no time. Unlike major existing simulators which are developed in hardware language description and make debugging very difficult, this high-level framework helps software designer, who need simpler means, to properly build mapping and scheduler algorithm then validate their contributions. This proposed toll is open source and extensible. The provided conceptual details allow users to efficiently create, validate their real scheduler and mapper as well as integrate it easily.

Systems-on-chip (SoC) have emerged as a key technology for most embedded systems, providing high flexibility and better performance. However, with the evolution of integrated circuit technology and the ever-increasing performance of electronic systems, SoCs became more complex. The designers of SoCs are embarking more and more IP (Intellectual Property) components to meet the needs of new applications, which results an increased communication costs. To adapt and remedy to this situation, Network-on-Chip (NoC) systems have emerged. They provide an alternative interconnection for chip multiprocessors to overcome limitations of legacy bus-based architectures. With the increased adoption of the above approach over time, a critical need for tools and systems design methodologies have emerged to evaluate the NoC architectures. Therefore, several works have focused in developing new NoC simulators. In this paper, we provide a survey around them in both 2D and 3D

— Systems-on-chip (SoC) have emerged as a key technology for most embedded systems, providing high flexibility and better performance. However, with the evolution of integrated circuit technology and the ever-increasing performance of electronic systems, SoCs became more complex. The designers of SoCs are embarking more and more IP (Intellectual Property) components to meet the needs of new applications, which resulted in an increased communication costs. To adapt and remedy to this situation, Network-on-Chip (NoC) systems have emerged. They provide an alternative interconnection for chip multiprocessors to overcome limitations of legacy bus-based architectures. With the increased adoption of the above approach over time, a critical need for tools and systems design methodologies have emerged to evaluate the NoC architectures. Therefore, several works have focused in developing new NoC simulators. In this paper, we provide a survey around them in both 2D and 3D architectures.

— The Network on-Chip (NoC) is considered as an emerging technology for distributed embedded systems which is proposed as an alternative interconnection solution in Mutli-Processors System on-Chip (MPSoC). This paper proposes a graphical toll that allows researchers to generate and configure quickly their Network on-Chip in the hope to evaluate easily their contributions in no time. Unlike major existing simulators which are developed in hardware language description and make debugging very difficult, this high-level framework helps software designer, who need simpler means, to properly build mapping and scheduler algorithm then validate their contributions. This proposed toll is open source and extensible. The provided conceptual details allow users to efficiently create, validate their real scheduler and mapper as well as integrate it easily.