Methods and models of a digital circuit analysis for test generation and fault simulation are off... more Methods and models of a digital circuit analysis for test generation and fault simulation are offered. The two-frame cubic algebra for compact cubic coverings of sequential primitive design, faulty and fault-free simulation of digital circuits is used. Problems of digital circuits testing are formalized as linear equations. The cubic method of primitive fault simulation, which allows: to transport input fault lists to primitive outputs; to generate analytical equations for digital circuit deductive simulation of the gate, functional and algorithmic description levels.
... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA ... more ... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA 2 PR 1 c min minn 1i i c c min minn 1i i c = ≥ ≥ = = 1) Generalized structure of Testbench synthesis [1] is represented in Fig. 2 and ...
... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA ... more ... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA 2 PR 1 c min minn 1i i c c min minn 1i i c = ≥ ≥ = = 1) Generalized structure of Testbench synthesis [1] is represented in Fig. 2 and ...
An exact method of memory elements diagnosis and repair by spares that enables to cover a set of ... more An exact method of memory elements diagnosis and repair by spares that enables to cover a set of fault cells by minimally possible quantity of spares is represented. The method is oriented on implementation to the Infrastructure Intellectual Property for SoC functionality. It enables to raise yield essentially on the electronic technology market by means of faulty chip repair in the process of production and operation, as well as to increase the life cycle duration of memory matrixes by repair of them in real time.
Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of S... more Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented.
2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007
method of digital device testability analysis, which represented on the system level (VHDL descri... more method of digital device testability analysis, which represented on the system level (VHDL description) as oriented graph for verification and test synthesis tasks simplification for fault coverage improving on the given test patterns is offered.
2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007
Existing software in Electronic Design Automation shows lack of dual-core processors support. As ... more Existing software in Electronic Design Automation shows lack of dual-core processors support. As a result, we see bad processing resources utilization. This work is devoted to exploration of existing approaches to parallel logic and fault simulation on dual-core workstations.
The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., 2003
Algebra-logical method of optimal memory repair based on the faults covering problem solving via ... more Algebra-logical method of optimal memory repair based on the faults covering problem solving via spare components using Boolean algebra is offered. The method enables to carry out the memory repair automatically in the operating process through embedded hardware or software implementation - a service infrastructure Intellectual Property module for fault repairing.
The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., 2003
Abstroc -A 'fast deductive-parallel backtraced fault simulation method uses the superposition pro... more Abstroc -A 'fast deductive-parallel backtraced fault simulation method uses the superposition procedure, which is oriented on.large digital designs. It is proposed processing of R T and gate level design representation.
2010 East-West Design & Test Symposium (EWDTS), 2010
The algebraic structure determining the vectormatrix transformation in the discrete vector Boolea... more The algebraic structure determining the vectormatrix transformation in the discrete vector Boolean space for the analyzing information based on logical operations on associative data.
Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), 2002
Models and procedures of test generation for digital systems verification based on genetic algori... more Models and procedures of test generation for digital systems verification based on genetic algorithms are offered.
2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007
... for RKHS Series Summation Vladimir Hahanov, Svetlana Chumachenko, Dmitriy Melnik, Alina Taran... more ... for RKHS Series Summation Vladimir Hahanov, Svetlana Chumachenko, Dmitriy Melnik, Alina Taran ... [14] Chumachenko S., Kirichenko L. RKHS-Methods at Series Summation for Software implementation // International Conferences on Information Theories and Applications. ...
Methods and models of a digital circuit analysis for test generation and fault simulation are off... more Methods and models of a digital circuit analysis for test generation and fault simulation are offered. The two-frame cubic algebra for compact cubic coverings of sequential primitive design, faulty and fault-free simulation of digital circuits is used. Problems of digital circuits testing are formalized as linear equations. The cubic method of primitive fault simulation, which allows: to transport input fault lists to primitive outputs; to generate analytical equations for digital circuit deductive simulation of the gate, functional and algorithmic description levels.
... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA ... more ... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA 2 PR 1 c min minn 1i i c c min minn 1i i c = ≥ ≥ = = 1) Generalized structure of Testbench synthesis [1] is represented in Fig. 2 and ...
... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA ... more ... functional modes (Pc): }. T,T, T,T, T,T,T,T{T , P)T(P;F)T(F RC 8 DF 7 ME 6 BS 5 AD 4 SP 3 SA 2 PR 1 c min minn 1i i c c min minn 1i i c = ≥ ≥ = = 1) Generalized structure of Testbench synthesis [1] is represented in Fig. 2 and ...
An exact method of memory elements diagnosis and repair by spares that enables to cover a set of ... more An exact method of memory elements diagnosis and repair by spares that enables to cover a set of fault cells by minimally possible quantity of spares is represented. The method is oriented on implementation to the Infrastructure Intellectual Property for SoC functionality. It enables to raise yield essentially on the electronic technology market by means of faulty chip repair in the process of production and operation, as well as to increase the life cycle duration of memory matrixes by repair of them in real time.
Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of S... more Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented.
2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007
method of digital device testability analysis, which represented on the system level (VHDL descri... more method of digital device testability analysis, which represented on the system level (VHDL description) as oriented graph for verification and test synthesis tasks simplification for fault coverage improving on the given test patterns is offered.
2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007
Existing software in Electronic Design Automation shows lack of dual-core processors support. As ... more Existing software in Electronic Design Automation shows lack of dual-core processors support. As a result, we see bad processing resources utilization. This work is devoted to exploration of existing approaches to parallel logic and fault simulation on dual-core workstations.
The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., 2003
Algebra-logical method of optimal memory repair based on the faults covering problem solving via ... more Algebra-logical method of optimal memory repair based on the faults covering problem solving via spare components using Boolean algebra is offered. The method enables to carry out the memory repair automatically in the operating process through embedded hardware or software implementation - a service infrastructure Intellectual Property module for fault repairing.
The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference., 2003
Abstroc -A 'fast deductive-parallel backtraced fault simulation method uses the superposition pro... more Abstroc -A 'fast deductive-parallel backtraced fault simulation method uses the superposition procedure, which is oriented on.large digital designs. It is proposed processing of R T and gate level design representation.
2010 East-West Design & Test Symposium (EWDTS), 2010
The algebraic structure determining the vectormatrix transformation in the discrete vector Boolea... more The algebraic structure determining the vectormatrix transformation in the discrete vector Boolean space for the analyzing information based on logical operations on associative data.
Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), 2002
Models and procedures of test generation for digital systems verification based on genetic algori... more Models and procedures of test generation for digital systems verification based on genetic algorithms are offered.
2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics, 2007
... for RKHS Series Summation Vladimir Hahanov, Svetlana Chumachenko, Dmitriy Melnik, Alina Taran... more ... for RKHS Series Summation Vladimir Hahanov, Svetlana Chumachenko, Dmitriy Melnik, Alina Taran ... [14] Chumachenko S., Kirichenko L. RKHS-Methods at Series Summation for Software implementation // International Conferences on Information Theories and Applications. ...
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