This research paper proposes a novel robust high-performance power spectrum estimator, and bispac... more This research paper proposes a novel robust high-performance power spectrum estimator, and bispactral power density analyzer that has outstanding capabilities in estimating noisy biomedical signal's power spectrum, and bispectrum. Biomedical signals usually are exposed to several sources of noises such as electrical noise from environmental noise from external sources, electrical equipment, and biological noise from the body. Therefore, accuracy and reliability are the most important feature of these systems in processing non-stationary biomedical signals. The proposed computationally-efficient architecture is based on a radix-8 memory-based 1024-point Blackman-Tuckey method power spectral density (PSD) estimator. The proposed nonparametric estimator uses a novel shared-resource CORDIC-II unit to avoid multiplications in FFT computation, as well as filtering operations implemented in folded architectures. In order to merge two FFTs, the module uses bidirectional fractional delay filters to estimate half delay samples. By using modified safe-scaling, valid final output would be achieved, without any averaging operation. The proposed and competing designs are implemented on Artix-7 FPGA which is an ideal option for DSP applications. As final results demonstrate, the hardware has a remarkable capability in operating in short word-lengths which allows high-performance in low-power applications to compute the power spectrum and bicoherence of a vital signal.
This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section o... more This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section of the architecture is based on a shared-resource improved coordinate rotation digital computer (CORDIC) unit, in an enhanced scalable DCT engine. To reduce the resources, and utilization area all micro-rotation operations have implemented as one united block in overlapped form. Using one processing element, the memory-based architecture has reduced the power consumption. Inputs and outputs of the processor are in-order which can be taken into account as an advantage for the proposed design. The processor has a low-complexity and distributed controller. Furthermore, due to the shared-resource implementation of CORDIC-II unit, by reduction of adding, shifting operations both in size, and number, the processor has high capabilities in short word lengths in comparison with state-of-the-art DCT processors. Compared to existing prominent DCT processors, the proposed processor achieves better results with limited hardware resources.
This paper proposes a novel method for the image interpolation problem based on two-dimensional d... more This paper proposes a novel method for the image interpolation problem based on two-dimensional discrete wavelet transform (DWT) with the edge preserving approach. The purpose of this method is to consider two contrasting issues of over-smoothing and creation of spurious edges at the same time, and offer a novel solution based on statistical dependencies of image sub-bands, and noise behavior. The offered method has a multi-faceted approach for the problem; by sub-band coding, it handles each 2D-DWT image sub-band with a different solution. For LH and HL sub-bands, two algorithms work together in order to preserve regularity. Area_Check algorithm is a four-phase edge-preserving algorithm that aims to recognize and interpolate separating lines of environments and edgy regions in the best possible way. On the other hand, RLS_AVG algorithm interpolates smooth surfaces of the image by keeping the regularity of the image without over-smoothing. In this regard, the offered algorithm has a...
This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estim... more This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estimator. The presented multiplier-less hardware uses a combined coefficient selection and shift-and-add implementation (CCSSI) unit in order to prevent multiplications in FFT computation. Two filtering operations, which are implemented in folded architecture, are utilized. The micro-rotation resources of the CCSSI unit can be shared with estimator’s modules simultaneously. The proposed architecture is a nonparametric estimator that operates based on a modified, memory-based, 128-point scalable radix-22 FFT processor. It uses bidirectional fractional delay filter to estimate half delay sample in merging two FFTs. Using modified safe-scaling, the final output would be valid, without any averaging operation. Another important feature of the proposed method is its capability of operating in short word lengths (WL). Artix-7, as an ideal option for DSP applications, is the utilized FPGA in this research. As results demonstrate, the hardware has a high capability in operating in short WLs which results in high performance in low-power applications.
This paper proposes a nonparametric approach with the purpose of estimating discrete wavelet tran... more This paper proposes a nonparametric approach with the purpose of estimating discrete wavelet transform (DWT) sub-band coefficients for high performance image interpolation. The number of clusters of defined statistical model that represents wavelet coefficients during the learning process is not fixed. The interpolating method is based on Hierarchical Dirichlet Process (HDP) where it uses the Blocked Gibbs Sampling method to obtain the optimum final values. The proposed HDP-HMM exploits statistical inter-scale, and intra-scale dependencies of image sub-bands of three-level decomposed 2D-DWT. It derives sub-bands of low resolution (LR) image, to obtain sub-bands of desired high resolution (HR) image. This research implements Hidden Markov model (HMM) to model the wavelet coefficients, and HDP to model the observations. It uses a very small size dataset that contains both LR and HR images of the dataset. The sophisticated statistical model introduced of the paper has excellent results in terms of Peak-to-Noise Ratio (PSNR), Structural Similarity Index (SSIM), Feature Similarity Index (FSIM), and Edge PSNR (EPSNR). It also has a great capability of repressing disturbing artifact, due to ability to model statistical dependencies of distant pixels. This method, and other compared state-of-the-art methods, have implemented on eighteen test-benches, with different statistical properties.
2019 27th Iranian Conference on Electrical Engineering (ICEE), 2019
Power spectrum analysis is a crucial matter in signal processing. In communication and biomedical... more Power spectrum analysis is a crucial matter in signal processing. In communication and biomedical signal processing, designing appropriate custom hardware for estimating signal is under everyday research. High frequency power spectrum estimator with embedded systems capabilities and for biomedical applications is the purpose of the current research. Nonparametric power spectral density estimation is the approach of this research in which no specific model is assumed in prior. This paper proposes a low power, high speed hardware with 125 MHz clock frequency rate, which its fast Fourier transform (FFT) engine is implemented with a radix-4 MDC structure. Bartlett method has been implemented in this research. The Artix-7 is the utilized FPGA in this research and VHDL is the used hardware design language. The proposed design computes Bartlett Power Spectral Density (PSD) estimation with only two added hardware units to a modified FFT engine. The offered limited power hardware performs we...
Discrete Cosine Transform (DCT) has an important role in image compression. This paper presents a... more Discrete Cosine Transform (DCT) has an important role in image compression. This paper presents a fast 2D-DCT architecture for hardware efficient embedded systems and power limited applications such as Internet of Things (IoT). The proposed design both from a structure point of view and operation reduction point of view has two headed approaches toward the problem of image and video compression. It includes a modified high speed architecture using an extra operational reducing technique. Reduction of operations occurs in two stages while computing 8-point DCT transform of the blocks. Defining the appropriate threshold for comparing DCT domain of two rows of an 8*8 block. Approximating DCT operations column-wise is the additional approach of the paper. The architecture is implemented on Xilinx Vivado 2018.2 with VHDL language on Artix-7 FPGA. 207 MHz clock frequency has achieved.
This paper has proposed a novel high performance image compression method based on Embedded Zerot... more This paper has proposed a novel high performance image compression method based on Embedded Zerotree Wavelet (EZW), which is a popular image compression coding scheme. Shortening the sweeping path according to the statistical properties of the image is the main issue that this paper has concentrated on. A developed statistical model based on hidden Markov model (HMM) and Gaussian mixture model (GMM) trains and produces the filter-bank coefficients of discrete wavelet transform (DWT). Custom design filter-banks for specific category of images, allow the encoder to pass a shorter route and stop at a closer point. This research proposes a novel image compression method based on an optimized EZW transform for three category of images, from statistically high to low correlated images. In each of these categories, the filter-banks are trained and extracted by their related GMM-HMM statistical models. The final results prove the efficiency of the method, and they are compared against the s...
This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a p... more This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a power spectral density (PSD) estimator, based on the Bartlett method, for low-power biomedical applications. The Bartlett method is a nonparametric method for PSD estimation. The proposed architecture operates based on a modified multiplierless 64-point optimized radix-22 single-path delay feedback (R22SDF) FFT processor. To obtain the final result, it also uses modified safe-scaling in a way that removes the need to use several extra hardware units. It takes advantage of combined coefficient selection and shift-and-add implementation (CCSSI) for computing twiddle factors which is a new algorithm based on digital computer coordinate rotation (CORDIC) for generating trigonometric values. The proposed method has the capability of operating on short word lengths (WLs). Artix-7 is the FPGA used in this research and Verilog is the language used for hardware design. For 8-bit WL and 244-mW powe...
This research paper proposes a novel robust high-performance power spectrum estimator, and bispac... more This research paper proposes a novel robust high-performance power spectrum estimator, and bispactral power density analyzer that has outstanding capabilities in estimating noisy biomedical signal's power spectrum, and bispectrum. Biomedical signals usually are exposed to several sources of noises such as electrical noise from environmental noise from external sources, electrical equipment, and biological noise from the body. Therefore, accuracy and reliability are the most important feature of these systems in processing non-stationary biomedical signals. The proposed computationally-efficient architecture is based on a radix-8 memory-based 1024-point Blackman-Tuckey method power spectral density (PSD) estimator. The proposed nonparametric estimator uses a novel shared-resource CORDIC-II unit to avoid multiplications in FFT computation, as well as filtering operations implemented in folded architectures. In order to merge two FFTs, the module uses bidirectional fractional delay filters to estimate half delay samples. By using modified safe-scaling, valid final output would be achieved, without any averaging operation. The proposed and competing designs are implemented on Artix-7 FPGA which is an ideal option for DSP applications. As final results demonstrate, the hardware has a remarkable capability in operating in short word-lengths which allows high-performance in low-power applications to compute the power spectrum and bicoherence of a vital signal.
This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section o... more This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section of the architecture is based on a shared-resource improved coordinate rotation digital computer (CORDIC) unit, in an enhanced scalable DCT engine. To reduce the resources, and utilization area all micro-rotation operations have implemented as one united block in overlapped form. Using one processing element, the memory-based architecture has reduced the power consumption. Inputs and outputs of the processor are in-order which can be taken into account as an advantage for the proposed design. The processor has a low-complexity and distributed controller. Furthermore, due to the shared-resource implementation of CORDIC-II unit, by reduction of adding, shifting operations both in size, and number, the processor has high capabilities in short word lengths in comparison with state-of-the-art DCT processors. Compared to existing prominent DCT processors, the proposed processor achieves better results with limited hardware resources.
This paper proposes a novel method for the image interpolation problem based on two-dimensional d... more This paper proposes a novel method for the image interpolation problem based on two-dimensional discrete wavelet transform (DWT) with the edge preserving approach. The purpose of this method is to consider two contrasting issues of over-smoothing and creation of spurious edges at the same time, and offer a novel solution based on statistical dependencies of image sub-bands, and noise behavior. The offered method has a multi-faceted approach for the problem; by sub-band coding, it handles each 2D-DWT image sub-band with a different solution. For LH and HL sub-bands, two algorithms work together in order to preserve regularity. Area_Check algorithm is a four-phase edge-preserving algorithm that aims to recognize and interpolate separating lines of environments and edgy regions in the best possible way. On the other hand, RLS_AVG algorithm interpolates smooth surfaces of the image by keeping the regularity of the image without over-smoothing. In this regard, the offered algorithm has a...
This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estim... more This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estimator. The presented multiplier-less hardware uses a combined coefficient selection and shift-and-add implementation (CCSSI) unit in order to prevent multiplications in FFT computation. Two filtering operations, which are implemented in folded architecture, are utilized. The micro-rotation resources of the CCSSI unit can be shared with estimator’s modules simultaneously. The proposed architecture is a nonparametric estimator that operates based on a modified, memory-based, 128-point scalable radix-22 FFT processor. It uses bidirectional fractional delay filter to estimate half delay sample in merging two FFTs. Using modified safe-scaling, the final output would be valid, without any averaging operation. Another important feature of the proposed method is its capability of operating in short word lengths (WL). Artix-7, as an ideal option for DSP applications, is the utilized FPGA in this research. As results demonstrate, the hardware has a high capability in operating in short WLs which results in high performance in low-power applications.
This paper proposes a nonparametric approach with the purpose of estimating discrete wavelet tran... more This paper proposes a nonparametric approach with the purpose of estimating discrete wavelet transform (DWT) sub-band coefficients for high performance image interpolation. The number of clusters of defined statistical model that represents wavelet coefficients during the learning process is not fixed. The interpolating method is based on Hierarchical Dirichlet Process (HDP) where it uses the Blocked Gibbs Sampling method to obtain the optimum final values. The proposed HDP-HMM exploits statistical inter-scale, and intra-scale dependencies of image sub-bands of three-level decomposed 2D-DWT. It derives sub-bands of low resolution (LR) image, to obtain sub-bands of desired high resolution (HR) image. This research implements Hidden Markov model (HMM) to model the wavelet coefficients, and HDP to model the observations. It uses a very small size dataset that contains both LR and HR images of the dataset. The sophisticated statistical model introduced of the paper has excellent results in terms of Peak-to-Noise Ratio (PSNR), Structural Similarity Index (SSIM), Feature Similarity Index (FSIM), and Edge PSNR (EPSNR). It also has a great capability of repressing disturbing artifact, due to ability to model statistical dependencies of distant pixels. This method, and other compared state-of-the-art methods, have implemented on eighteen test-benches, with different statistical properties.
2019 27th Iranian Conference on Electrical Engineering (ICEE), 2019
Power spectrum analysis is a crucial matter in signal processing. In communication and biomedical... more Power spectrum analysis is a crucial matter in signal processing. In communication and biomedical signal processing, designing appropriate custom hardware for estimating signal is under everyday research. High frequency power spectrum estimator with embedded systems capabilities and for biomedical applications is the purpose of the current research. Nonparametric power spectral density estimation is the approach of this research in which no specific model is assumed in prior. This paper proposes a low power, high speed hardware with 125 MHz clock frequency rate, which its fast Fourier transform (FFT) engine is implemented with a radix-4 MDC structure. Bartlett method has been implemented in this research. The Artix-7 is the utilized FPGA in this research and VHDL is the used hardware design language. The proposed design computes Bartlett Power Spectral Density (PSD) estimation with only two added hardware units to a modified FFT engine. The offered limited power hardware performs we...
Discrete Cosine Transform (DCT) has an important role in image compression. This paper presents a... more Discrete Cosine Transform (DCT) has an important role in image compression. This paper presents a fast 2D-DCT architecture for hardware efficient embedded systems and power limited applications such as Internet of Things (IoT). The proposed design both from a structure point of view and operation reduction point of view has two headed approaches toward the problem of image and video compression. It includes a modified high speed architecture using an extra operational reducing technique. Reduction of operations occurs in two stages while computing 8-point DCT transform of the blocks. Defining the appropriate threshold for comparing DCT domain of two rows of an 8*8 block. Approximating DCT operations column-wise is the additional approach of the paper. The architecture is implemented on Xilinx Vivado 2018.2 with VHDL language on Artix-7 FPGA. 207 MHz clock frequency has achieved.
This paper has proposed a novel high performance image compression method based on Embedded Zerot... more This paper has proposed a novel high performance image compression method based on Embedded Zerotree Wavelet (EZW), which is a popular image compression coding scheme. Shortening the sweeping path according to the statistical properties of the image is the main issue that this paper has concentrated on. A developed statistical model based on hidden Markov model (HMM) and Gaussian mixture model (GMM) trains and produces the filter-bank coefficients of discrete wavelet transform (DWT). Custom design filter-banks for specific category of images, allow the encoder to pass a shorter route and stop at a closer point. This research proposes a novel image compression method based on an optimized EZW transform for three category of images, from statistically high to low correlated images. In each of these categories, the filter-banks are trained and extracted by their related GMM-HMM statistical models. The final results prove the efficiency of the method, and they are compared against the s...
This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a p... more This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a power spectral density (PSD) estimator, based on the Bartlett method, for low-power biomedical applications. The Bartlett method is a nonparametric method for PSD estimation. The proposed architecture operates based on a modified multiplierless 64-point optimized radix-22 single-path delay feedback (R22SDF) FFT processor. To obtain the final result, it also uses modified safe-scaling in a way that removes the need to use several extra hardware units. It takes advantage of combined coefficient selection and shift-and-add implementation (CCSSI) for computing twiddle factors which is a new algorithm based on digital computer coordinate rotation (CORDIC) for generating trigonometric values. The proposed method has the capability of operating on short word lengths (WLs). Artix-7 is the FPGA used in this research and Verilog is the language used for hardware design. For 8-bit WL and 244-mW powe...
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