The focus of the paper is detection of faults in NoC routers by combining concurrent checkers wit... more The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage constraints. The stress is in particular on the minimization of the error detection latency, which is a crucial aspect in order to eliminate (or limit) error propagation. Second, the concurrent checkers will be complemented by embedded on-line test packets which are to be applied as a periodic routine during the idle periods in router operation. The framework together with the corresponding methodology has been successfully applied to a realistic case-study of a fault tolerant NoC router design. The case study shows that combining concurrent routers with embedded test allows reducing the area overhead of the checkers from 31--35% down to 1.5--10% without sacrificing the fault coverage.
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. T... more The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied ...
... Jaan Raik Vineeth Govind Raimund Ubar Tallinn University of Technology, Department of Compute... more ... Jaan Raik Vineeth Govind Raimund Ubar Tallinn University of Technology, Department of Computer Engineering E-mail: {jaan|vineeth|raiub}@pld.ttu.ee ... We don't have to consider the general case of wiring because in NoCs we are dealing with regular layout structures, where ...
Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the com... more Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the communication network according to the routing algorithm implemented. However, the extreme scaling of emerging nanometer technologies makes the routers vulnerable to wear-out and environmental effects. In order to contain this issue, development of online testing capabilities for the NoC routers is a must. This paper proposes concurrent online checkers for structural faults in the NoC routing algorithms utilizing the Logic-Based Distributed Routing (LBDR) concept. We show by fault injection experiments that the fault coverage of existing checking mechanisms for LBDR faults is very low. We propose an extended set of concurrent checkers that increase the coverage more than threefold facilitating detection of the majority of structural faults within the LBDR.
Page 1. RT-Level Test Point Insertion for Sequential Circuits Jaan Raik Vineeth Govind Tallinn Un... more Page 1. RT-Level Test Point Insertion for Sequential Circuits Jaan Raik Vineeth Govind Tallinn University of Technology Royal Institute of Technology, Stockholm bund Ubax Tallinn University of Technology Abstract ... kt F={ fi, . . . , fn} be a set of faults in the circuit, T = {tl, . . . , ...
Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the com... more Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the communication network according to the routing algorithm implemented. However, the extreme scaling of emerging nanometer technologies makes the routers vulnerable to wear-out and environmental effects. In order to contain this issue, development of online testing capabilities for the NoC routers is a must. This paper proposes concurrent online checkers for structural faults in the NoC routing algorithms utilizing the Logic-Based Distributed Routing (LBDR) concept. We show by fault injection experiments that the fault coverage of existing checking mechanisms for LBDR faults is very low. We propose an extended set of concurrent checkers that increase the coverage more than threefold facilitating detection of the majority of structural faults within the LBDR.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
The focus of the paper is detection of faults in NoC routers by combining concurrent checkers wit... more The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage constraints. The stress is in particular on the minimization of the error detection latency, which is a crucial aspect in order to eliminate (or limit) error propagation. Second, the concurrent checkers will be complemented by embedded on-line test packets which are to be applied as a periodic routine during the idle periods in router operation. The framework together with the corresponding methodology has been successfully applied to a realistic case-study of a fault tolerant NoC router design. The case study shows that combining concurrent routers with embedded test allows reducing the area overhead of the checkers from 31--35% down to 1.5--10% without sacrificing the fault coverage.
2012 International Symposium on System on Chip (SoC), 2012
ABSTRACT This paper aims at devising an optimized pseudo-random test methodology for NoCs and its... more ABSTRACT This paper aims at devising an optimized pseudo-random test methodology for NoCs and its architectural support. The guiding principle consists of using a test pattern compaction engine for generating minimal test lengths. We show the application of this principle driven by the objective to minimize test application time, at the cost of test wrapper complexity. The achieved design point results in a reduction of test application time by two orders of magnitude with respect to state-of-the-art test architectures for NoCs exploiting pseudo-random patterns.
First International Workshop onTestability Assessment, 2004. IWoTA 2004. Proceedings.
Page 1. RT-Level Test Point Insertion for Sequential Circuits Jaan Raik Vineeth Govind Tallinn Un... more Page 1. RT-Level Test Point Insertion for Sequential Circuits Jaan Raik Vineeth Govind Tallinn University of Technology Royal Institute of Technology, Stockholm bund Ubax Tallinn University of Technology Abstract ... kt F={ fi, . . . , fn} be a set of faults in the circuit, T = {tl, . . . , ...
... Jaan Raik Vineeth Govind Raimund Ubar Tallinn University of Technology, Department of Compute... more ... Jaan Raik Vineeth Govind Raimund Ubar Tallinn University of Technology, Department of Computer Engineering E-mail: {jaan|vineeth|raiub}@pld.ttu.ee ... We don't have to consider the general case of wiring because in NoCs we are dealing with regular layout structures, where ...
Over the past few years, Network-on-a-Chip (NoC) has become increasingly popular as a scalable in... more Over the past few years, Network-on-a-Chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing, diagnosis and debug strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on Design-for-Testability (DfT) approaches based on switch wrappers (e.g. [1, 2]) and there is a lack of test algorithms dedicated to on-chip networks. In there earlier works [3, 4] the authors of this paper have developed a well scalable test method, which targets structural faults in NoCs by external tests applied from the boundaries of the network. The external test method [4] is based on a functional fault model for switch’s registers and multiplexers. The tests are organized into three types of configurations (straight paths, turning paths and resource interaction, respectively), which will cover the entire fault model. Our method is applicable for deflecting (FIFOless) switches supporting deterministic (i.e. XY) routing, which are compatible with the concepts developed e.g. in the NOSTRUM concept [5]. We have shown that the new method is well scalable and produces a test set whose volume grows linearly with the rank of the network matrix. For an n×n network between 53-112 n clock cycles will be required to test all the full switching network. This is far less than in any of the previous DfT based approaches. The stuck-at fault coverage achieved by such an external test is nearly 100 %. The goal of current work is to introduce a method for diagnosing faults in individual links of the network switches using external tests and functional models.
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. T... more The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied ...
The focus of the paper is detection of faults in NoC routers by combining concurrent checkers wit... more The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage constraints. The stress is in particular on the minimization of the error detection latency, which is a crucial aspect in order to eliminate (or limit) error propagation. Second, the concurrent checkers will be complemented by embedded on-line test packets which are to be applied as a periodic routine during the idle periods in router operation. The framework together with the corresponding methodology has been successfully applied to a realistic case-study of a fault tolerant NoC router design. The case study shows that combining concurrent routers with embedded test allows reducing the area overhead of the checkers from 31--35% down to 1.5--10% without sacrificing the fault coverage.
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. T... more The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied ...
... Jaan Raik Vineeth Govind Raimund Ubar Tallinn University of Technology, Department of Compute... more ... Jaan Raik Vineeth Govind Raimund Ubar Tallinn University of Technology, Department of Computer Engineering E-mail: {jaan|vineeth|raiub}@pld.ttu.ee ... We don't have to consider the general case of wiring because in NoCs we are dealing with regular layout structures, where ...
Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the com... more Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the communication network according to the routing algorithm implemented. However, the extreme scaling of emerging nanometer technologies makes the routers vulnerable to wear-out and environmental effects. In order to contain this issue, development of online testing capabilities for the NoC routers is a must. This paper proposes concurrent online checkers for structural faults in the NoC routing algorithms utilizing the Logic-Based Distributed Routing (LBDR) concept. We show by fault injection experiments that the fault coverage of existing checking mechanisms for LBDR faults is very low. We propose an extended set of concurrent checkers that increase the coverage more than threefold facilitating detection of the majority of structural faults within the LBDR.
Page 1. RT-Level Test Point Insertion for Sequential Circuits Jaan Raik Vineeth Govind Tallinn Un... more Page 1. RT-Level Test Point Insertion for Sequential Circuits Jaan Raik Vineeth Govind Tallinn University of Technology Royal Institute of Technology, Stockholm bund Ubax Tallinn University of Technology Abstract ... kt F={ fi, . . . , fn} be a set of faults in the circuit, T = {tl, . . . , ...
Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the com... more Network on Chips (NoCs) are composed of routers, whose task is to dispatch packets within the communication network according to the routing algorithm implemented. However, the extreme scaling of emerging nanometer technologies makes the routers vulnerable to wear-out and environmental effects. In order to contain this issue, development of online testing capabilities for the NoC routers is a must. This paper proposes concurrent online checkers for structural faults in the NoC routing algorithms utilizing the Logic-Based Distributed Routing (LBDR) concept. We show by fault injection experiments that the fault coverage of existing checking mechanisms for LBDR faults is very low. We propose an extended set of concurrent checkers that increase the coverage more than threefold facilitating detection of the majority of structural faults within the LBDR.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
The focus of the paper is detection of faults in NoC routers by combining concurrent checkers wit... more The focus of the paper is detection of faults in NoC routers by combining concurrent checkers with embedded on-line test to enable cost-effective trade-offs between area-overhead and test coverage. First, we propose a framework of tools for formally evaluating the quality of the checkers and for optimizing the overhead area with given fault coverage constraints. The stress is in particular on the minimization of the error detection latency, which is a crucial aspect in order to eliminate (or limit) error propagation. Second, the concurrent checkers will be complemented by embedded on-line test packets which are to be applied as a periodic routine during the idle periods in router operation. The framework together with the corresponding methodology has been successfully applied to a realistic case-study of a fault tolerant NoC router design. The case study shows that combining concurrent routers with embedded test allows reducing the area overhead of the checkers from 31--35% down to 1.5--10% without sacrificing the fault coverage.
2012 International Symposium on System on Chip (SoC), 2012
ABSTRACT This paper aims at devising an optimized pseudo-random test methodology for NoCs and its... more ABSTRACT This paper aims at devising an optimized pseudo-random test methodology for NoCs and its architectural support. The guiding principle consists of using a test pattern compaction engine for generating minimal test lengths. We show the application of this principle driven by the objective to minimize test application time, at the cost of test wrapper complexity. The achieved design point results in a reduction of test application time by two orders of magnitude with respect to state-of-the-art test architectures for NoCs exploiting pseudo-random patterns.
First International Workshop onTestability Assessment, 2004. IWoTA 2004. Proceedings.
Page 1. RT-Level Test Point Insertion for Sequential Circuits Jaan Raik Vineeth Govind Tallinn Un... more Page 1. RT-Level Test Point Insertion for Sequential Circuits Jaan Raik Vineeth Govind Tallinn University of Technology Royal Institute of Technology, Stockholm bund Ubax Tallinn University of Technology Abstract ... kt F={ fi, . . . , fn} be a set of faults in the circuit, T = {tl, . . . , ...
... Jaan Raik Vineeth Govind Raimund Ubar Tallinn University of Technology, Department of Compute... more ... Jaan Raik Vineeth Govind Raimund Ubar Tallinn University of Technology, Department of Computer Engineering E-mail: {jaan|vineeth|raiub}@pld.ttu.ee ... We don't have to consider the general case of wiring because in NoCs we are dealing with regular layout structures, where ...
Over the past few years, Network-on-a-Chip (NoC) has become increasingly popular as a scalable in... more Over the past few years, Network-on-a-Chip (NoC) has become increasingly popular as a scalable interconnect infrastructure for IP cores. Simultaneously to developing new design paradigms, testing, diagnosis and debug strategies for such network architectures have to be considered. The previous works on testing NoCs have been mainly based on Design-for-Testability (DfT) approaches based on switch wrappers (e.g. [1, 2]) and there is a lack of test algorithms dedicated to on-chip networks. In there earlier works [3, 4] the authors of this paper have developed a well scalable test method, which targets structural faults in NoCs by external tests applied from the boundaries of the network. The external test method [4] is based on a functional fault model for switch’s registers and multiplexers. The tests are organized into three types of configurations (straight paths, turning paths and resource interaction, respectively), which will cover the entire fault model. Our method is applicable for deflecting (FIFOless) switches supporting deterministic (i.e. XY) routing, which are compatible with the concepts developed e.g. in the NOSTRUM concept [5]. We have shown that the new method is well scalable and produces a test set whose volume grows linearly with the rank of the network matrix. For an n×n network between 53-112 n clock cycles will be required to test all the full switching network. This is far less than in any of the previous DfT based approaches. The stuck-at fault coverage achieved by such an external test is nearly 100 %. The goal of current work is to introduce a method for diagnosing faults in individual links of the network switches using external tests and functional models.
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. T... more The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied ...
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