This paper investigates embedding Energy Storage (ES) with multiple wind turbines in order to del... more This paper investigates embedding Energy Storage (ES) with multiple wind turbines in order to deliver to the grid a smooth and constant power as demanded by the system operator. The demand power is shared by DFIGs proportional to their ratings utilizing classical voltage and frequency droop characteristics. The paper addresses the system control methodologies for delivering constant power to the
2008 11th IEEE High Assurance Systems Engineering Symposium, 2008
This paper presents a soft error-tolerant architecture to protect embedded processors register fi... more This paper presents a soft error-tolerant architecture to protect embedded processors register files. The proposed architecture is based on selectively duplication of the most vulnerable registers values in a cache memory embedded beside the processor register file so called register cache. To do this, two parity bits are added to each register of the processor to detect up to three
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008
In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (s... more In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (single event transient and upset robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch
2011 18th IEEE International Conference on Electronics, Circuits, and Systems, 2011
ABSTRACT This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a... more ABSTRACT This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition.
The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012
ABSTRACT This paper presents a fault tolerant routing algorithm for injured hypercube. The propos... more ABSTRACT This paper presents a fault tolerant routing algorithm for injured hypercube. The proposed routing algorithm backtracks from the faulty nodes using stacks of passed nodes embedded in the header of messages. When a node receives a new message, a set of possible destinations for the message is formed using the mentioned stack. This helps the receiving node to detect its adjacent faulty nodes and to prevent the message to pass through the corresponding links. In this way, the proposed algorithm efficiently works with any number of faulty nodes in the network. Deadlock freedom of the proposed routing algorithm is obtained by the lowest possible requirements i.e., one virtual channel per each physical channel. In order to evaluate the proposed routing algorithm, a 7-dimentional hypercube network is simulated in various conditions i.e., different traffic rates, different number of faulty nodes, and different message lengths. Simulation results confirm that the proposed routing algorithm in comparison with the previously proposed routings: 1) provides an average of 20% improvement in the performance of the network, and 2) increases the reliability of the network.
The 5th Conference on Information and Knowledge Technology, 2013
ABSTRACT A large amount of energy in nodes of a Wireless Sensor Network (WSN) is consumed due to ... more ABSTRACT A large amount of energy in nodes of a Wireless Sensor Network (WSN) is consumed due to the inner-network communications. In this paper, an energy efficient routing algorithm is proposed which saves a significant portion of inner-network communications energy. To do this, the proposed routing algorithm selects sensor nodes with higher residual energy, more neighbors, and lower distance from the Base Station (BS) as Cluster Head (CH) nodes. Then, it manages sensor nodes appropriately and constructs clusters such a way to maximize WSN lifetime and minimize average energy dissipation per each sensor node. To evaluate the proposed routing algorithm, various simulations have been carried out by using of MATLAB simulator. The proposed routing algorithm is compared to the previous proposed algorithms e.g., LEACH, DBS, and LEACH-C algorithms. Results of the simulations show that the proposed routing algorithm has been improved the WSN performance at least 65%, reduces the energy consumption of the WSN up to 62%, and improves the successfully delivered packet ratio by at least 56% as compared to the previous routing algorithms.
2008 Third International Conference on Availability, Reliability and Security, 2008
This paper proposes a new technique called CFEDC to detect and correct control flow errors (CFEs)... more This paper proposes a new technique called CFEDC to detect and correct control flow errors (CFEs) without program interruption. The proposed technique is based on the modification of application software and minor changes in the underlying hardware. To demonstrate the ...
2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010
Abstract In this paper, we propose a very fast analytical approach to measure the overall circuit... more Abstract In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an error site to primary outputs as well as system bistables. Then, we perform a multi-cycle error propagation analysis in the sequential circuit. The results show that the proposed approach is four to five orders of magnitude faster than the Monte Carlo (MC) simulation-based fault ...
The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012
ABSTRACT In this paper, we propose a low power register file architecture for embedded processors... more ABSTRACT In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, ”Value-Aware Partitioned Register File (VAP-RF)”, employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure.
2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013
ABSTRACT ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use... more ABSTRACT ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integrates a multi-priority mapping algorithm with a hybrid SPM structure. The proposed structure divides SPM into three parts: 1) a part is equipped with Non-Volatile Memory (NVM) which is immune against soft errors, 2) a part is equipped with Error-Correcting Code, and 3) a part is equipped with parity. The proposed mapping algorithm is responsible to distribute the program blocks among the above three parts with regards to their vulnerability level. The simulation results demonstrate that the FTSPM reduces the SPM vulnerability by about 7x in comparison to a pure SRAM-based SPM. In addition, the dynamic energy consumption of the proposed method is 77% and 47% less than that of a pure NVM-based SPM and a pure SRAM-based SPM, respectively.
This paper investigates embedding Energy Storage (ES) with multiple wind turbines in order to del... more This paper investigates embedding Energy Storage (ES) with multiple wind turbines in order to deliver to the grid a smooth and constant power as demanded by the system operator. The demand power is shared by DFIGs proportional to their ratings utilizing classical voltage and frequency droop characteristics. The paper addresses the system control methodologies for delivering constant power to the
2008 11th IEEE High Assurance Systems Engineering Symposium, 2008
This paper presents a soft error-tolerant architecture to protect embedded processors register fi... more This paper presents a soft error-tolerant architecture to protect embedded processors register files. The proposed architecture is based on selectively duplication of the most vulnerable registers values in a cache memory embedded beside the processor register file so called register cache. To do this, two parity bits are added to each register of the processor to detect up to three
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008
In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (s... more In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (single event transient and upset robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch
2011 18th IEEE International Conference on Electronics, Circuits, and Systems, 2011
ABSTRACT This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a... more ABSTRACT This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition.
The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012
ABSTRACT This paper presents a fault tolerant routing algorithm for injured hypercube. The propos... more ABSTRACT This paper presents a fault tolerant routing algorithm for injured hypercube. The proposed routing algorithm backtracks from the faulty nodes using stacks of passed nodes embedded in the header of messages. When a node receives a new message, a set of possible destinations for the message is formed using the mentioned stack. This helps the receiving node to detect its adjacent faulty nodes and to prevent the message to pass through the corresponding links. In this way, the proposed algorithm efficiently works with any number of faulty nodes in the network. Deadlock freedom of the proposed routing algorithm is obtained by the lowest possible requirements i.e., one virtual channel per each physical channel. In order to evaluate the proposed routing algorithm, a 7-dimentional hypercube network is simulated in various conditions i.e., different traffic rates, different number of faulty nodes, and different message lengths. Simulation results confirm that the proposed routing algorithm in comparison with the previously proposed routings: 1) provides an average of 20% improvement in the performance of the network, and 2) increases the reliability of the network.
The 5th Conference on Information and Knowledge Technology, 2013
ABSTRACT A large amount of energy in nodes of a Wireless Sensor Network (WSN) is consumed due to ... more ABSTRACT A large amount of energy in nodes of a Wireless Sensor Network (WSN) is consumed due to the inner-network communications. In this paper, an energy efficient routing algorithm is proposed which saves a significant portion of inner-network communications energy. To do this, the proposed routing algorithm selects sensor nodes with higher residual energy, more neighbors, and lower distance from the Base Station (BS) as Cluster Head (CH) nodes. Then, it manages sensor nodes appropriately and constructs clusters such a way to maximize WSN lifetime and minimize average energy dissipation per each sensor node. To evaluate the proposed routing algorithm, various simulations have been carried out by using of MATLAB simulator. The proposed routing algorithm is compared to the previous proposed algorithms e.g., LEACH, DBS, and LEACH-C algorithms. Results of the simulations show that the proposed routing algorithm has been improved the WSN performance at least 65%, reduces the energy consumption of the WSN up to 62%, and improves the successfully delivered packet ratio by at least 56% as compared to the previous routing algorithms.
2008 Third International Conference on Availability, Reliability and Security, 2008
This paper proposes a new technique called CFEDC to detect and correct control flow errors (CFEs)... more This paper proposes a new technique called CFEDC to detect and correct control flow errors (CFEs) without program interruption. The proposed technique is based on the modification of application software and minor changes in the underlying hardware. To demonstrate the ...
2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010
Abstract In this paper, we propose a very fast analytical approach to measure the overall circuit... more Abstract In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an error site to primary outputs as well as system bistables. Then, we perform a multi-cycle error propagation analysis in the sequential circuit. The results show that the proposed approach is four to five orders of magnitude faster than the Monte Carlo (MC) simulation-based fault ...
The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012), 2012
ABSTRACT In this paper, we propose a low power register file architecture for embedded processors... more ABSTRACT In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, ”Value-Aware Partitioned Register File (VAP-RF)”, employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure.
2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013
ABSTRACT ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use... more ABSTRACT ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integrates a multi-priority mapping algorithm with a hybrid SPM structure. The proposed structure divides SPM into three parts: 1) a part is equipped with Non-Volatile Memory (NVM) which is immune against soft errors, 2) a part is equipped with Error-Correcting Code, and 3) a part is equipped with parity. The proposed mapping algorithm is responsible to distribute the program blocks among the above three parts with regards to their vulnerability level. The simulation results demonstrate that the FTSPM reduces the SPM vulnerability by about 7x in comparison to a pure SRAM-based SPM. In addition, the dynamic energy consumption of the proposed method is 77% and 47% less than that of a pure NVM-based SPM and a pure SRAM-based SPM, respectively.
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