Shah Jahan Wani

Images are being processed and manipulated at every step with the help of modern multimedia tools. In most gaming devices and cartoon series, movement of images are confined or restricted to right, left, up & down directions only. Cellular automata can be ...

Nanotechnology based QCA basic logic layouts work well while simulating on QCA Designer software. The design of half adders has been reported by various researchers and most of the circuit combinations produce excellent results on simulation. Although design of QCA full adders has been reported by a large number of researchers but the simulation results on most of the circuits fail to produce claimed outputs as such the carry forward work is becoming difficult. There are certain difficulties in producing desired simulation results while joining two half adders to design full adder. The main cause for the problem seems to be the mismatch of input data, when earlier stage data is combined with the forward stage. We have tried to study some full adder designs on the basis of simulation results to move forward with our own designs for the purpose. With analysis of few reported adders we have proposed two full adder circuit layout designs with analysis for efficient implementation and future improvements.

Nanotechnology based QCA basic logic layouts work well while simulating on QCA Designer software. The design of half adders has been reported by various researchers and most of the circuit combinations produce excellent results on simulation. Although design of QCA full adders has been reported by a large number of researchers but the simulation results on most of the circuits fail to produce claimed outputs as such the carry forward work is becoming difficult. There are certain difficulties in producing desired simulation results while joining two half adders to design full adder. The main cause for the problem seems to be the mismatch of input data, when earlier stage data is combined with the forward stage. We have tried to study some full adder designs on the basis of simulation results to move forward with our own designs for the purpose. With analysis of few reported adders we have proposed two full adder circuit layout designs with analysis for efficient implementation and future improvements.

Cellular Automata rules producing evolution type phenomena have been used for a wide range of applications. Various models have been designed and explored for different applications. Although the strength of its parallelism has been felt by various researchers but its exploration for applications will not minimize the hardware but also maximize the optimum strength of processors. Our present study was intended to identify the additive 2D Cellular Automata linear rules on the quality of pattern evolution and the periodic parallelism utilization. We have made an analysis of 2DCA linear game of life (GOL) rule in Neumann neighborhood pattern evolution and observed pattern multiplication in the process. The results achieved will not only minimize the required hardware for parallel channel creation but also expand the microcomputer processing horizon.

In the fast growing information and communication technology (ICT) challenge of data
security is emerging out predominantly due to flow of vital data on the wired and wireless networks.
Cryptosystems have been designed with various techniques of text encryption and decryption. Easy key
encryptions have low level of attack immunity while as complex keys although more resistant to attacks
have other drawbacks of occupying more memory space and low speed of encoding and decoding.
Cryptosystems have been designed with the help of pseudo sequence generation property of cellular
automata too and found relevant due to easy VLSI implementation. We have observed a large number of 2 -
dimensional cellular automata linear rules in odd groups having an ability to generate the original data in
the forward iterations of applied rule. This property is having a versatile fitness for cryptographic
applications. Since almost all additive CA linear rules have been found to have irreversible character both
encryption and decryption of data are possible in forward direction with the difference of iterations only.
The model we can call as Pattern Cryptography, like other CA based models provides easy VLSI
implementation with elegant properties of compact size, high efficiency and high speed at low cost. Since
all odd groups contain such rules to achieve the cryptographic objectives, although with varied
complexity, an additional feature of varied complexity can be incorporated in its VLSI design
implementation.

Images are being processed and manipulated at every step with the help of modern multimedia tools. In most gaming devices and cartoon series, movement of images are confined or restricted to right, left, up & down directions only. Cellular automata can be successfully applied in image processing. Cellular Automata is a methodology that uses discrete space to represent the state of each element of a domain and this state can be changed according to a transition rule. With our scheme, we are not only able to translate the image into x and y-axis, but also diagonal translations can be achieved. Uniform cellular automata rules are constructed to transform the images in all the directions

Quantum-dot Cellular Automata (QCA) based circuit designs have been explored since its concept development in early 1980’s. Although there are lot of implementation barriers for the development of this nanotechnology to work smoothly at room temperature but the simulated circuit implementations have attracted a large number of researchers towards this new field. The success of metal dot implementation even at very low temperatures has paved a way for exploring new possibilities in computing paradigm. An ample of circuit layouts have been proposed for the design of EX-OR gate, a vital element for arithmetic processes. We have analyzed some reported layouts in terms of their simulation accuracy, latency, cell count and noise performance to propose few single layer robust circuits for their efficient implementation.