Abstract
Traditional memory technologies, such as SRAM, suffer from limited package density and high leakage power. Applications are getting increasingly memory hungry in the age of big data. Non-volatile memories such as STTRAM, PCM, and ReRAM emerged as attractive contenders to replace traditional SRAM-based memories. They have high density and zero leakage power. However, they have a limited write endurance. Non-uniform write patterns in applications can shorten the life of non-volatile memories. Traditional cache block replacement strategy like LRU leads some cache blocks to be accessed more frequently than others, accelerating the wear out of the cache. We present a Write-Aware Last Level Non-Volatile Cache (WALL-NVC), which improves the lifetime up to 5.84\(\times \) for uni-core, 3.34\(\times \) for dual-core, and 4.11\(\times \) for quad-core systems. It reduces intraset write variation in last level caches up to 98.91%, 90.11%, and 94.12% for uni-core, dual-core, and quad-core systems, respectively, using write distribution and NVM-friendly replacement mechanism.
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Sivakumar, S., Mannampalli, M., Jose, J. (2023). Enhancing Lifetime of Non-volatile Memory Caches by Write-Aware Techniques. In: Giri, C., Iizuka, T., Rahaman, H., Bhattacharya, B.B. (eds) Emerging Electronic Devices, Circuits and Systems. Lecture Notes in Electrical Engineering, vol 1004. Springer, Singapore. https://doi.org/10.1007/978-981-99-0055-8_10
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DOI: https://doi.org/10.1007/978-981-99-0055-8_10
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