Abstract
This paper describes an ultralow power consumption and ultra-small area all-digital phase-locked loop (ADPLL) for system-on-chip (SoC) applications. In the ADPLL, a dual-tuned digitally controlled oscillator (DCO) and dual-tuned locking algorithm are presented. The proposed DCO consists of a digital-to-analog converter (DAC) control array with a coarse-tuned stage and a fine-tuned stage. The different control codes for DAC array can be used as coarse-tuning code or fine-tuning code depending on the situation. The whole circuit is automatically place-and-routed (P&R) by a digital design flow. Fabricated in a 55-nm standard CMOS process, this ADPLL occupies only 34 \(\upmu \)m\( \times \) 24 \(\upmu \)m core area, which to the best knowledge of the authors is the smallest phase-locked loop published so far. The experimental results indicate a fast locking process of the entire system. At the DCO frequency of 3 GHz, the power consumption is 112.32 \(\upmu \)W with a 1.0-V supply voltage, and the root-mean-square jitter is 14.4 ps at 100 MHz pre-divider output frequency.
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This work was supported by the National Key Technologies Research and Development Program of China (2018YFB0904900, 2018YFB0904902).
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Zhang, P., Su, Y. & Yang, Y. A 0.001-mm\(^{2}\) 112.32-\(\upmu \)W All-Digital PLL with Dual-Tuned DCO and Dual-Tuned Control Algorithm. Circuits Syst Signal Process 41, 1563–1576 (2022). https://doi.org/10.1007/s00034-021-01838-y
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DOI: https://doi.org/10.1007/s00034-021-01838-y