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A Schmitt-Trigger-Based Low-Voltage 11 T SRAM Cell for Low-Leakage in 7-nm FinFET Technology

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Abstract

This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell’s stability performance increases. The proposed SRAM cell’s leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell’s write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology.

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The data will be shared on request to the corresponding author.

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Acknowledgements

Erfan Abbasian and Morteza Gholipour acknowledge the funding support of Babol Noshirvani University of Technology through grant program No. BNUT/389023/1400.

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Authors and Affiliations

  1. Faculty of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran

    Erfan Abbasian & Morteza Gholipour

  2. Department of Electronics and Communication Engineering, Government College of Engineering, Srirangam, Trichy, Tamilnadu, India

    Elangovan Mani

  3. Department of Electrical and Electronics Engineering, Shiraz University of Technology, Shiraz, Iran

    Mehrzad Karamimanesh

  4. Department of Electronics and Communication Engineering, Mewat Engineering College, Nuh, Haryana, India

    Mohd Sahid & Adil Zaidi

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  1. Erfan Abbasian
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  2. Elangovan Mani
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  4. Mehrzad Karamimanesh
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Correspondence to Elangovan Mani.

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Abbasian, E., Mani, E., Gholipour, M. et al. A Schmitt-Trigger-Based Low-Voltage 11 T SRAM Cell for Low-Leakage in 7-nm FinFET Technology. Circuits Syst Signal Process 41, 3081–3105 (2022). https://doi.org/10.1007/s00034-021-01950-z

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