Abstract
CMOS circuits based on scaled transistors are typically more susceptible to soft errors caused by energetic particles in the radiation environment than circuits employing their large-area counterparts. In this paper, a soft error tolerant latch built on a Schmitt trigger, which is entirely realized with NMOS transistors with an additional voltage booster, which we refer to as NST-VB, is proposed. To evaluate the circuits’ radiation resilience, we identify the most sensitive nodes by analyzing the critical charges at the various latches’ internal sensitive nodes. We also examine the linear energy transfer (LET) of the essential latches and observe that the NST-VB latch has an improved LET of \(0.386~\mathrm {MeV~cm^2/mg}\) as compared to \(0.231~\mathrm {MeV~cm^2/mg}\) and \(0.365~\mathrm {MeV~cm^2/mg}\) for unhardened latch and ST latch, respectively. For the process variation analysis, we further examined 5k Monte Carlo simulations to analyze the impact of device variability on our design and observe that the proposed NST-VB latch has \(1.96\times \) less variability critical voltage concerning the ST latch. Further, the logic flipping probability for NST-VB latch is 48.32% compared to 53.04% for ST latch. Also, the critical charge to power delay area product ratio (QPAR) is calculated and evaluated for the proposed latch’s effectiveness compared to other considered latches.
Similar content being viewed by others
Data availability statement
All data is provided in the results section of this paper.
References
Liang, H., Wang, Z., Huang, Z., & Yan, A. (2014). Design of a radiation hardened latch for low-power circuits. In IEEE 23rd Asian test symposium (pp. 19–24). IEEE.
Huang, Z., Liang, H., & Hellebrand, S. (2015). A high performance SEU tolerant latch. Journal of Electronic Testing, 31(4), 349–359.
Detcheverry, C., Dachs, C., Lorfevre, E., Sudre, C., Bruguier, G., Palau, J., Gasiot, J., & Ecoffet, R. (1997). SEU critical charge and sensitive area in a submicron CMOS technology. IEEE Transactions on Nuclear Science, 44(6), 2266–2273.
Yan, A., Liang, H., Huang, Z., Jiang, C., Ouyang, Y., & Li, X. (2016). An SEU resilient, set filterable and cost effective latch in presence of PVT variations. Microelectronics Reliability, 63, 239–250.
Sajjade, F. M., Goyal, N. K., Varaprasad, B., & Moogina, R. (2018). Radiation hardened by design latches: A review and SEU fault simulations. Microelectronics Reliability, 83, 127–135.
Qi, C., Xiao, L., Guo, J., & Wang, T. (2015). Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology. Microelectronics Reliability, 55(6), 863–872.
Schrimpf, R., Warren, K., Weller, R., Reed, R., Massengill, L., Alles, M., et al. (2008). Reliability and radiation effects in IC technologies. In IEEE international reliability physics symposium (pp. 97–106). IEEE.
Tang, D., He, C., Li, Y., Zang, H., Xiong, C., & Zhang, J. (2014). Soft error reliability in advanced CMOS technologies-trends and challenges. Science China Technological Sciences, 57(9), 1846–1857.
Seifert, N., Gill, B., Pellish, J. A., Marshall, P. W., & LaBel, K. A. (2011). The susceptibility of 45 and 32 nm bulk CMOS latches to low-energy protons. IEEE Transactions on Nuclear Science, 58(6), 2711–2718.
Ibe, E., Taniguchi, H., Yahagi, Y., Shimbo, K.-I., & Toba, T. (2010). Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule. IEEE Transactions on Electron Devices, 57(7), 1527–1538.
Ziegler, J. F. (1996). Terrestrial cosmic rays. IBM Journal of Research and Development, 40(1), 19–39.
Baggio, J., Ferlet-Cavrois, V., Duarte, H., & Flament, O. (2004). Analysis of proton/neutron SEU sensitivity of commercial SRAMs-application to the terrestrial environment test method. IEEE Transactions on Nuclear Science, 51(6), 3420–3426.
Nan, H., & Choi, K. (2011). Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology. Microelectronics Reliability, 51(12), 2086–2092.
Calin, T., Nicolaidis, M., & Velazco, R. (1996). Upset hardened memory design for submicron CMOS technology. IEEE Transactions on Nuclear Science, 43(6), 2874–2878.
Sasaki, Y., Namba, K., & Ito, H. (2008). Circuit and latch capable of masking soft errors with Schmitt trigger. Journal of Electronic Testing, 24(1–3), 11–19.
Lin, S., Kim, Y.-B., & Lombardi, F. (2010). Design and performance evaluation of radiation hardened latches for nanoscale CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(7), 1315–1319.
Moghaddam, M., Moaiyeri, M. H., & Eshghi, M. (2017). Design and evaluation of an efficient Schmitt trigger-based hardened latch in CNTFET technology. IEEE Transactions on Device and Materials Reliability, 17(1), 267–277.
Nan, H., & Choi, K. (2012). Low cost and highly reliable hardened latch design for nanoscale CMOS technology. Microelectronics Reliability, 52(6), 1209–1214.
Omaña, M., Rossi, D., & Metra, C. (2007). Latch susceptibility to transient faults and new hardening approach. IEEE Transactions on Computers, 56(9), 1255–1268.
Sasaki, Y., Namba, K., & Ito, H. (2006). Soft error masking circuit and latch using Schmitt trigger circuit. In 1st IEEE international symposium on defect and fault tolerance in VLSI systems (pp. 327–335). IEEE.
Lin, S., Kim, Y.-B., & Lombardi, F. (2009). Soft-error hardening designs of nanoscale CMOS latches. In 27th IEEE VLSI test symposium (pp. 41–46). IEEE.
Asli, R. N., & Shirinzadeh, S. (2013). High efficiency time redundant hardened latch for reliable circuit design. Journal of Electronic Testing, 29(4), 537–544.
Melek, L. A. P., da Silva, A. L., Schneider, M. C., & Galup-Montoro, C. (2017). Analysis and design of the classical CMOS Schmitt trigger in subthreshold operation. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(4), 869–878.
Shah, A. P., Yadav, N., Beohar, A., & Vishvakarma, S. K. (2018). Process variation and NBTI resilient Schmitt trigger for stable and reliable circuits. IEEE Transactions on Device and Materials Reliability, 18(4), 546–554.
Shah, A. P., Rossi, D., Sharma, V., Vishvakarma, S. K., & Waltl, M. (2020). Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit. Microelectronics Reliability, 107, 113617.
Predictive Technology Model (PTM). (2017). Retrieved December 12, 2017, from http://ptm.asu.edu/.
Synopsys. (2010). Hspice user guide: Simulation and analysis.
Yang, F. L., & Saleh, R. A. (1992). Simulation and analysis of transient faults in digital circuits. IEEE Journal of Solid-State Circuits, 27(3), 258–264.
Jahinuzzaman, S. M., Sharifkhani, M., & Sachdev, M. (2009). An analytical model for soft error critical charge of nanometric SRAMs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(9), 1187–1195.
Sayil, S. (2016). Single event soft error mechanisms. In S. Sayil (Ed.), Soft error mechanisms. Modeling and mitigation (pp. 31–48). Springer.
Black, D. A., Robinson, W. H., Wilcox, I. Z., Limbrick, D. B., & Black, J. D. (2015). Modeling of single event transients with dual double-exponential current sources: Implications for logic cell characterization. IEEE Transactions on Nuclear Science, 62(4), 1540–1549.
Alouani, I., Elsharkasy, W. M., Eltawil, A. M., Kurdahi, F. J., & Niar, S. (2017). As8-static random access memory (SRAM): Asymmetric SRAM architecture for soft error hardening enhancement. IET Circuits, Devices & Systems, 11(1), 89–94.
Ding, Q., Luo, R., Wang, H., Yang, H., & Xie, Y. (2006). Modeling the impact of process variation on critical charge distribution. In IEEE international SOC conference (pp. 243–246). IEEE.
Shah, A. P., Vishvakarma, S. K., & Hübner, M. (2020). Soft error hardened asymmetric 10t SRAM cell for aerospace applications. Journal of Electronic Testing, 36, 255–269.
Shah, A. P., & Waltl, M. (2019). Low cost and high performance radiation hardened latch design for reliable circuits. In 2019 IEEE 26th international conference on electronics circuits and systems (pp. 197–200). IEEE.
Wang, F., & Agrawal, V. D. (2008). Single event upset: An embedded tutorial. In 21st international conference on VLSI design (VLSID) (pp. 429–434). IEEE.
Acknowledgements
The research leading to this work has received substantial funding from the Take-off program of the Austrian Research Promotion Agency FFG (Projects Nos. 861022 and 867414).
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Shah, A.P., Gupta, N. & Waltl, M. High-performance radiation hardened NMOS only Schmitt Trigger based latch designs. Analog Integr Circ Sig Process 109, 657–671 (2021). https://doi.org/10.1007/s10470-021-01924-w
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-021-01924-w