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A memristor-based Bayesian machine

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Abstract

Memristors, and other emerging memory technologies, can be used to create energy-efficient implementations of neural networks. However, for certain edge applications (in which there is access to limited amounts of data and where explainable decisions are required), neural networks may not provide an acceptable form of intelligence. Bayesian reasoning could resolve these concerns, but it is computationally expensive and—unlike neural networks—does not naturally translate to memristor-based architectures. Here we report a memristor-based Bayesian machine. The architecture of the machine is obtained by writing Bayes’ law in a way that makes its implementation natural by the principles of distributed memory and stochastic computing, allowing the circuit to function solely using local memory and minimal data movement. We fabricate a prototype circuit that incorporates 2,048 memristors and 30,080 transistors using a hybrid complementary metal–oxide–semiconductor/memristor process. We show that a scaled-up design of the machine is more energy efficient in a practical gesture recognition task than a standard implementation of Bayesian inference on a microcontroller unit. Our Bayesian machine also offers instant on/off operation and is resilient to single-event upsets.

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Fig. 1: General architecture of a Bayesian machine.
Fig. 2: Fabricated memristor-based Bayesian machine.
Fig. 3: Measurements of the fabricated memristor-based Bayesian machine.
Fig. 4: Application of the Bayesian machine on a practical gesture recognition task.

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Data availability

The analysed datasets and all data measured in this study are available from the corresponding author upon reasonable request.

Code availability

The software programs used for modelling the Bayesian machine are available from the corresponding author upon reasonable request.

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Acknowledgements

This work was supported by the European Research Council starting grant NANOINFER (reference: 715872). We would like to thank A. Cherkaoui, M. Faix, R. Frisch, J. Grollier, L. Herrera-Diez, E. Mazer, A. Renaudineau, J. Simatic and S. Tiwari for discussion and invaluable feedback.

Author information

Author notes

  1. These authors contributed equally: Kamel-Eddine Harabi, Tifenn Hirtzlin, Clément Turck.

Authors and Affiliations

  1. Université Paris-Saclay, CNRS, Centre de Nanosciences et de Nanotechnologies, Palaiseau, France

    Kamel-Eddine Harabi, Tifenn Hirtzlin, Clément Turck & Damien Querlioz

  2. Université Grenoble-Alpes, CEA-LETI, Grenoble, France

    Tifenn Hirtzlin & Elisa Vianello

  3. HawAI.tech, Grenoble, France

    Raphaël Laurent & Jacques Droulez

  4. Sorbonne Université, CNRS, Institut des Systèmes Intelligents et de Robotique, Paris, France

    Jacques Droulez & Pierre Bessière

  5. Aix-Marseille Université, CNRS, Institut Matériaux Microélectronique Nanosciences de Provence, Marseille, France

    Jean-Michel Portal & Marc Bocquet

Authors
  1. Kamel-Eddine Harabi
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Contributions

K.-E.H and T.H. designed the test chip, under the supervision of J.-M.P and D.Q. J.-M.P. designed the mixed-signal circuits of the test chip. M.B. and T.H. performed the electrical characterization of the system. K.-E.H. and C.T. designed the scaled-up version of the system. R.L. developed the gesture recognition application, and C.T. adapted it to the memristor-based Bayesian machine. J.D. and P.B. developed the initial theory of the Bayesian machine. E.V. led the fabrication of the test chip. D.Q. supervised the work and wrote the initial version of the manuscript. All the authors discussed the results and reviewed the manuscript.

Corresponding author

Correspondence to Damien Querlioz.

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Nature Electronics thanks Hussam Amrouch, Justin Correll and Rajkumar Kubendran for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 Detailed operation of the Bayesian machine.

a Schematic illustrating the detailed architecture of a likelihood elementary block. b Flowchart of the different operations to perform a Bayesian inference computation in the Bayesian machine. c Time diagram illustrating the operation of the Bayesian machine. This Figure is described in detail in Supplementary Note 4.

Extended Data Table 1 Comparison of the design choices of the Bayesian machine with leading emerging memory-based realizations of neural network hardware blocks. Abbreviations. RBM: restricted Boltzmann machine. MAC: multiply and accumulate. PCM: Phase Change Memory. ADC: analog-to-digital converter. CDS: correlated double sampling. SLC: single-level cell. TDC: time-to-digital converter. Predet.: Predetermined. ND: not discussed. The content of this Table is discussed extensively within Supplementary Note 12
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Supplementary information

Supplementary Information

Supplementary Notes 1–12, Figs. 1–14 and Tables 1 and 2.

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Harabi, KE., Hirtzlin, T., Turck, C. et al. A memristor-based Bayesian machine. Nat Electron 6, 52–63 (2023). https://doi.org/10.1038/s41928-022-00886-9

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