Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content
Springer Nature Link
Log in

Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

The objective of this work is to minimize testing cost of analog and RF circuits for which complete specification tests are available. We use an integer linear program (ILP) to eliminate as many tests as possible without exceeding the required defect level. The method leverages correlation among specifications, thereby avoiding the tests for specifications that are sufficiently covered by tests for other specifications. First, Monte Carlo simulation determines probabilities for each test covering all other specifications it was not originally intended for. These probabilities and the given defect level then define an ILP model for eliminating unnecessary tests. An hypothetical example illustration of ten specifications demonstrates that depending on the defect level requirement up to half of the tests may be eliminated. Monte Carlo simulation using spice for probabilistic characterization of tests versus specifications followed by ILP optimization for two commercially available integrated circuits, an operational amplifier and a radio frequency power controller (RFPC), are presented as evidence of effectiveness of the technique.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

References

  1. Asratian AS, Denley TMJ, Häggkvist R (1998) Bipartite graphs and their applications. Cambridge University Press. Tracts in Mathematics 131

  2. Biswas S, Blanton RD (2008) Test compaction for mixed-signal circuits using pass-fail test data. In: Proc. 26th IEEE VLSI Test Symposium, 299–308

  3. Biswas S, Li P, Blanton R D, Pileggi L T (2005) Specification test compaction for analog circuits and MEMS [Accelerometer and Opamp Examples]. In: Proc. IEEE Design, Automation and Test in Europe, 164–169

  4. Brockman JB, Director SW (1989) Predictive subset testing: Optimizing IC parametric performance testing for quality, cost, and yield. IEEE Trans Semicond Manuf 2(3):104–113

    Article  Google Scholar 

  5. Burns M, Roberts G (2000) Introduction to Mixed-Signal IC Test and Measurement. Oxford University Press, New York

    Google Scholar 

  6. Bushnell ML, Agrawal VD (2000) Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Springer, Boston

    Google Scholar 

  7. Chang H.-M, Cheng K-T, Zhang W, Li X, Butler KM (2011) Test cost reduction through performance prediction using virtual probe. In: Proc. International Test Conference, 1–9. Paper 1.3

  8. Devarayanadurg G, Soma M, Goteti P, Huynh SD (1999) Test set selection for structural faults in analog IC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18(7):1026–1039

    Article  Google Scholar 

  9. International Technology Roadmap for Semiconductors (ITRS) 2009 (2015) http://bit.ly/1cCvuY3

  10. Kaminska B (1999) Is analog fault simulation a key to product quality? practical considerations. In: Proc. International Test Conference, 648–648

  11. Kuhn K J (2010) CMOS transistor scaling past 32nm and implications on variation

  12. Kupp N, Drineas P, Slamani M, Makris Y (2008) Confidence estimation in Non-RF to RF correlation-based specification test compaction. In: Proc. IEEE European Test Symposium, 35–40

  13. Kupp N, Huang K, Carulli J M, Makris Y (2012) Spatial correlation modeling for probe test cost reduction in RF devices. In: Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 23–29

  14. LP Solve (2015) http://sourceforge.net/projects/lpsolve/

  15. LTC 4400 Datasheet – RF Power Controllers with 450kHz Loop BW and 45dB Dynamic Range (2015) Linear Technology, http://cds.linear.com/docs/en/datasheet/4400fas.pdf

  16. Lu N. C-C, Gerzberg L, Lu C-Y, Meindl JD (1981) Modeling and optimization of monolithic polycrystalline silicon resistors. IEEE Trans on Electron Devices 28(7):818–830

    Article  Google Scholar 

  17. Milor L, Sangiovanni-Vincentelli AL (1994) Minimizing production test time to detect faults in analog circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13(6):796–813

    Article  Google Scholar 

  18. Nagi N, Chatterjee A, Yoon H, Abraham JA (1998) Signature analysis for analog and mixed-signal circuit test response compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(6):540–546

    Article  Google Scholar 

  19. Niknejad A M, Meyer R G (1997) Analysis and Optimization of Monolithic Inductors and Transformers for RF ICs. In: Proc. IEEE Custom Integrated Circuits Conference, 375–378

  20. Razavi B (1999) CMOS technology characterization for analog and RF design. IEEE Journal of Solid-State Circuits 34(3):268–276

    Article  Google Scholar 

  21. Schaub KB, Kelly J (2004) Production testing of RF and system-on-a-chip devices for wireless communications. Boston: Artech House

  22. Sindia S, Agrawal V D (2014) Specification test minimization for given defect level. In: Proc. IEEE Latin American Test Workshop, 1–6

  23. Stratigopoulos H, Drineas P, Slamani M, Makris Y (2010) RF specification test compaction using learning machines. IEEE Trans on Very Large Scale Integration (VLSI) Systems 18(6):998–1002

    Article  Google Scholar 

  24. Stratigopoulos H-G, Drineas P, Slamani M, Makris Y (2007) Non-RF to RF test correlation using learning machines: A case study. In: Proc. 25th IEEE VLSI Test Symposium, 9–14

  25. Stratogopoulos H-G, Sunter S (2014) Efficient monte Carlo-based analog parametric fault modelling. In: Proc. 32nd IEEE VLSI Test Symposium, 1–6

  26. The Spice Page (2015) http://bit.ly/1b72tyv

  27. TI LM 741 Datasheet (2015) http://www.ti.com/lit/ds/symlink/lm741.pdf

  28. TI LM 741 SPICE model (2015) http://www.ti.com/lit/zip/snom211

  29. Tuinhout HP, Elzinga H, Brugman JTH, Postma F (1995) Accurate Capacitor Matching Measurements using Floating Gate Test Structures. In: Proc. International Conference on Microelectronic Test Structures, 133–137

  30. Variyam PN, Cherubal S, Chatterjee A (2002) Prediction of analog performance parameters using fast transient testing. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems 21(3):349–361

    Article  Google Scholar 

  31. Yelten MB, Franzon PD, Steer MB (2011) Surrogate-model-based analysis of analog circuits – Part I: Variability analysis. IEEE Transactions on Device and Materials Reliability 11(3):458–465

    Article  Google Scholar 

  32. Yelten MB, Natarajan S, Xue B, Goteti P (2013) Scalable and efficient analog parametric fault identification. In: Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 387–392

  33. Zhang W, Li X, Liu F, Acar E, Rutenbar RA, Blanton RD (2011) Virtual probe: A statistical framework for low-cost silicon characterization of nanoscale integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30(12):1814–1827

    Article  Google Scholar 

Download references

Acknowledgments

The authors thank Dr. R. A. Parekhji for suggesting the problem of specification based test minimization and for his interest in this work. This research is supported in part by the National Science Foundation Grants CNS-0708962, CCF-1116213 and IIP-0738088.

Author information

Authors and Affiliations

  1. Intel Corporation, Hillsboro, OR, 97124, USA

    Suraj Sindia

  2. ECE Department, Auburn University, Auburn, AL, 36849, USA

    Vishwani D. Agrawal

Authors
  1. Suraj Sindia
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vishwani D. Agrawal
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vishwani D. Agrawal.

Additional information

Responsible Editor: L. M. Bolzani Pöhls

Work described here was performed while S. Sindia was with the Department of Electrical and Computer Engineering, Auburn University, Auburn, AL 36849, USA. Ideas in this research were first presented at the 15th IEEE Latin-American Test Workshop, Fortaleza, Brazil, March 12-15, 2014 [22].

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sindia, S., Agrawal, V.D. Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. J Electron Test 31, 479–489 (2015). https://doi.org/10.1007/s10836-015-5545-1

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-015-5545-1

Keywords

Search

Navigation